tiled              83 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
tiled             622 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
tiled             366 drivers/gpu/drm/exynos/exynos_drm_fimc.c static void fimc_src_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled)
tiled             408 drivers/gpu/drm/exynos/exynos_drm_fimc.c 	if (tiled)
tiled             632 drivers/gpu/drm/exynos/exynos_drm_fimc.c static void fimc_dst_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled)
tiled             681 drivers/gpu/drm/exynos/exynos_drm_fimc.c 	if (tiled)
tiled             449 drivers/gpu/drm/exynos/exynos_drm_gsc.c static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
tiled             515 drivers/gpu/drm/exynos/exynos_drm_gsc.c 	if (tiled)
tiled             636 drivers/gpu/drm/exynos/exynos_drm_gsc.c static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
tiled             702 drivers/gpu/drm/exynos/exynos_drm_gsc.c 	if (tiled)
tiled             228 drivers/gpu/drm/i915/gvt/dmabuf.c 		switch (p.tiled) {
tiled             245 drivers/gpu/drm/i915/gvt/dmabuf.c 			gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled);
tiled             147 drivers/gpu/drm/i915/gvt/fb_decoder.c 	u32 tiled, int stride_mask, int bpp)
tiled             155 drivers/gpu/drm/i915/gvt/fb_decoder.c 		switch (tiled) {
tiled             175 drivers/gpu/drm/i915/gvt/fb_decoder.c 				tiled);
tiled             219 drivers/gpu/drm/i915/gvt/fb_decoder.c 		plane->tiled = val & PLANE_CTL_TILED_MASK;
tiled             234 drivers/gpu/drm/i915/gvt/fb_decoder.c 		plane->tiled = val & DISPPLANE_TILED;
tiled             258 drivers/gpu/drm/i915/gvt/fb_decoder.c 	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
tiled             428 drivers/gpu/drm/i915/gvt/fb_decoder.c 	plane->tiled = !!(val & SPRITE_TILED);
tiled             104 drivers/gpu/drm/i915/gvt/fb_decoder.h 	u32	tiled;		/* tiling mode: linear, X-tiled, Y tiled, etc */
tiled             119 drivers/gpu/drm/i915/gvt/fb_decoder.h 	u8	tiled;		/* X-tiled */
tiled            1182 drivers/gpu/drm/omapdrm/omap_gem.c 		tiler_align(gem2fmt(flags), &gsize.tiled.width,
tiled            1183 drivers/gpu/drm/omapdrm/omap_gem.c 			    &gsize.tiled.height);
tiled            1185 drivers/gpu/drm/omapdrm/omap_gem.c 		size = tiler_size(gem2fmt(flags), gsize.tiled.width,
tiled            1186 drivers/gpu/drm/omapdrm/omap_gem.c 				  gsize.tiled.height);
tiled            1188 drivers/gpu/drm/omapdrm/omap_gem.c 		omap_obj->width = gsize.tiled.width;
tiled            1189 drivers/gpu/drm/omapdrm/omap_gem.c 		omap_obj->height = gsize.tiled.height;
tiled            2382 drivers/gpu/drm/radeon/r600_cs.c 	u32 header, cmd, count, tiled;
tiled            2398 drivers/gpu/drm/radeon/r600_cs.c 		tiled = GET_DMA_T(header);
tiled            2407 drivers/gpu/drm/radeon/r600_cs.c 			if (tiled) {
tiled            2438 drivers/gpu/drm/radeon/r600_cs.c 			if (tiled) {
tiled              87 drivers/gpu/drm/radeon/radeon_fb.c int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled)
tiled              90 drivers/gpu/drm/radeon/radeon_fb.c 	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
tiled             989 drivers/gpu/drm/radeon/radeon_mode.h int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
tiled             271 drivers/gpu/drm/sun4i/sun4i_frontend.c 	bool tiled = (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED);
tiled             279 drivers/gpu/drm/sun4i/sun4i_frontend.c 		*val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR
tiled             284 drivers/gpu/drm/sun4i/sun4i_frontend.c 		*val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR
tiled              61 include/uapi/drm/omap_drm.h 	} tiled;		/* (for tiled formats) */