tile_width 1953 drivers/gpu/drm/i915/display/intel_display.c unsigned int *tile_width, tile_width 1959 drivers/gpu/drm/i915/display/intel_display.c *tile_width = tile_width_bytes / cpp; tile_width 2216 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_width, tile_width 2223 drivers/gpu/drm/i915/display/intel_display.c unsigned int pitch_pixels = pitch_tiles * tile_width; tile_width 2233 drivers/gpu/drm/i915/display/intel_display.c *x += tiles % pitch_tiles * tile_width; tile_width 2260 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_size, tile_width, tile_height; tile_width 2264 drivers/gpu/drm/i915/display/intel_display.c intel_tile_dims(fb, color_plane, &tile_width, &tile_height); tile_width 2268 drivers/gpu/drm/i915/display/intel_display.c swap(tile_width, tile_height); tile_width 2270 drivers/gpu/drm/i915/display/intel_display.c pitch_tiles = pitch / (tile_width * cpp); tile_width 2273 drivers/gpu/drm/i915/display/intel_display.c intel_adjust_tile_offset(x, y, tile_width, tile_height, tile_width 2330 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_size, tile_width, tile_height; tile_width 2334 drivers/gpu/drm/i915/display/intel_display.c intel_tile_dims(fb, color_plane, &tile_width, &tile_height); tile_width 2338 drivers/gpu/drm/i915/display/intel_display.c swap(tile_width, tile_height); tile_width 2340 drivers/gpu/drm/i915/display/intel_display.c pitch_tiles = pitch / (tile_width * cpp); tile_width 2346 drivers/gpu/drm/i915/display/intel_display.c tiles = *x / tile_width; tile_width 2347 drivers/gpu/drm/i915/display/intel_display.c *x %= tile_width; tile_width 2352 drivers/gpu/drm/i915/display/intel_display.c intel_adjust_tile_offset(x, y, tile_width, tile_height, tile_width 2660 drivers/gpu/drm/i915/display/intel_display.c int tile_width, tile_height; tile_width 2664 drivers/gpu/drm/i915/display/intel_display.c intel_tile_dims(fb, i, &tile_width, &tile_height); tile_width 2665 drivers/gpu/drm/i915/display/intel_display.c tile_width *= hsub; tile_width 2668 drivers/gpu/drm/i915/display/intel_display.c ccs_x = (x * hsub) % tile_width; tile_width 2670 drivers/gpu/drm/i915/display/intel_display.c main_x = intel_fb->normal[0].x % tile_width; tile_width 2718 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_width, tile_height; tile_width 2722 drivers/gpu/drm/i915/display/intel_display.c intel_tile_dims(fb, i, &tile_width, &tile_height); tile_width 2725 drivers/gpu/drm/i915/display/intel_display.c rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); tile_width 2726 drivers/gpu/drm/i915/display/intel_display.c rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); tile_width 2747 drivers/gpu/drm/i915/display/intel_display.c rot_info->plane[i].width * tile_width, tile_width 2755 drivers/gpu/drm/i915/display/intel_display.c swap(tile_width, tile_height); tile_width 2762 drivers/gpu/drm/i915/display/intel_display.c tile_width, tile_height, tile_width 2832 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_width, tile_height; tile_width 2838 drivers/gpu/drm/i915/display/intel_display.c intel_tile_dims(fb, i, &tile_width, &tile_height); tile_width 2859 drivers/gpu/drm/i915/display/intel_display.c tile_width * cpp); tile_width 2860 drivers/gpu/drm/i915/display/intel_display.c info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); tile_width 2872 drivers/gpu/drm/i915/display/intel_display.c info->plane[i].width * tile_width, tile_width 2882 drivers/gpu/drm/i915/display/intel_display.c swap(tile_width, tile_height); tile_width 2885 drivers/gpu/drm/i915/display/intel_display.c plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp; tile_width 2893 drivers/gpu/drm/i915/display/intel_display.c tile_width, tile_height, tile_width 121 drivers/gpu/drm/i915/gem/i915_gem_tiling.c unsigned int tile_width; tile_width 149 drivers/gpu/drm/i915/gem/i915_gem_tiling.c tile_width = 128; tile_width 151 drivers/gpu/drm/i915/gem/i915_gem_tiling.c tile_width = 512; tile_width 153 drivers/gpu/drm/i915/gem/i915_gem_tiling.c if (!stride || !IS_ALIGNED(stride, tile_width)) tile_width 365 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h u16 tile_width; tile_width 255 drivers/gpu/drm/radeon/r600_cs.c u32 tile_width = 8; tile_width 259 drivers/gpu/drm/radeon/r600_cs.c u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples; tile_width 277 drivers/gpu/drm/radeon/r600_cs.c *pitch_align = max((u32)tile_width, tile_width 285 drivers/gpu/drm/radeon/r600_cs.c *pitch_align = max((u32)macro_tile_width * tile_width, tile_width 287 drivers/gpu/drm/radeon/r600_cs.c (values->blocksize * values->nsamples * tile_width))); tile_width 508 drivers/staging/media/allegro-dvt/allegro-core.c s32 tile_width[4];