tile_size 155 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) tile_size 157 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (tile_size == dm_256k_tile) tile_size 159 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c else if (tile_size == dm_64k_tile) tile_size 155 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) tile_size 157 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (tile_size == dm_256k_tile) tile_size 159 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c else if (tile_size == dm_64k_tile) tile_size 132 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) tile_size 134 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (tile_size == dm_256k_tile) tile_size 136 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c else if (tile_size == dm_64k_tile) tile_size 196 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) tile_size 198 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (tile_size == dm_256k_tile) tile_size 200 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c else if (tile_size == dm_64k_tile) tile_size 5386 drivers/gpu/drm/drm_edid.c w = tile->tile_size[0] | tile->tile_size[1] << 8; tile_size 5387 drivers/gpu/drm/drm_edid.c h = tile->tile_size[2] | tile->tile_size[3] << 8; tile_size 2218 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_size, tile_size 2226 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(old_offset & (tile_size - 1)); tile_size 2227 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(new_offset & (tile_size - 1)); tile_size 2230 drivers/gpu/drm/i915/display/intel_display.c tiles = (old_offset - new_offset) / tile_size; tile_size 2260 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_size, tile_width, tile_height; tile_size 2263 drivers/gpu/drm/i915/display/intel_display.c tile_size = intel_tile_size(dev_priv); tile_size 2274 drivers/gpu/drm/i915/display/intel_display.c tile_size, pitch_tiles, tile_size 2330 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_size, tile_width, tile_height; tile_size 2333 drivers/gpu/drm/i915/display/intel_display.c tile_size = intel_tile_size(dev_priv); tile_size 2349 drivers/gpu/drm/i915/display/intel_display.c offset = (tile_rows * pitch_tiles + tiles) * tile_size; tile_size 2353 drivers/gpu/drm/i915/display/intel_display.c tile_size, pitch_tiles, tile_size 2637 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_size = intel_tile_size(dev_priv); tile_size 2714 drivers/gpu/drm/i915/display/intel_display.c tile_size); tile_size 2715 drivers/gpu/drm/i915/display/intel_display.c offset /= tile_size; tile_size 2763 drivers/gpu/drm/i915/display/intel_display.c tile_size, pitch_tiles, tile_size 2764 drivers/gpu/drm/i915/display/intel_display.c gtt_offset_rotated * tile_size, 0); tile_size 2776 drivers/gpu/drm/i915/display/intel_display.c x * cpp, tile_size); tile_size 2783 drivers/gpu/drm/i915/display/intel_display.c if (mul_u32_u32(max_size, tile_size) > obj->base.size) { tile_size 2785 drivers/gpu/drm/i915/display/intel_display.c mul_u32_u32(max_size, tile_size), obj->base.size); tile_size 2802 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_size = intel_tile_size(dev_priv); tile_size 2854 drivers/gpu/drm/i915/display/intel_display.c DRM_MODE_ROTATE_0, tile_size); tile_size 2855 drivers/gpu/drm/i915/display/intel_display.c offset /= tile_size; tile_size 2894 drivers/gpu/drm/i915/display/intel_display.c tile_size, pitch_tiles, tile_size 2895 drivers/gpu/drm/i915/display/intel_display.c gtt_offset * tile_size, 0); tile_size 72 include/drm/drm_displayid.h u8 tile_size[4];