tile_mode 2841 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.tile_mode = tile_mode 151 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.tile_mode, tile_mode 243 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.tile_mode, tile_mode 360 drivers/gpu/drm/amd/display/dc/dc_hw_types.h enum tile_mode_values tile_mode; tile_mode 379 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c GRPH_MICRO_TILE_MODE, info->gfx8.tile_mode, tile_mode 186 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c set_reg_field_value(value, info->gfx8.tile_mode, tile_mode 196 drivers/gpu/drm/nouveau/nouveau_bo.c u32 tile_mode, u32 tile_flags) tile_mode 248 drivers/gpu/drm/nouveau/nouveau_bo.c nvbo->mode = tile_mode; tile_mode 321 drivers/gpu/drm/nouveau/nouveau_bo.c uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, tile_mode 328 drivers/gpu/drm/nouveau/nouveau_bo.c nvbo = nouveau_bo_alloc(cli, &size, &align, flags, tile_mode, tile_mode 75 drivers/gpu/drm/nouveau/nouveau_bo.h u32 flags, u32 tile_mode, u32 tile_flags); tile_mode 79 drivers/gpu/drm/nouveau/nouveau_bo.h u32 tile_mode, u32 tile_flags, struct sg_table *sg, tile_mode 169 drivers/gpu/drm/nouveau/nouveau_gem.c uint32_t tile_mode, uint32_t tile_flags, tile_mode 187 drivers/gpu/drm/nouveau/nouveau_gem.c nvbo = nouveau_bo_alloc(cli, &size, &align, flags, tile_mode, tile_mode 246 drivers/gpu/drm/nouveau/nouveau_gem.c rep->tile_mode = nvbo->mode; tile_mode 268 drivers/gpu/drm/nouveau/nouveau_gem.c req->info.domain, req->info.tile_mode, tile_mode 16 drivers/gpu/drm/nouveau/nouveau_gem.h uint32_t domain, uint32_t tile_mode, tile_mode 150 drivers/video/fbdev/via/via-core.c u32 tile_mode; /* "tile mode" setting */ tile_mode 260 drivers/video/fbdev/via/via-core.c descr->tile_mode = 0; tile_mode 55 include/uapi/drm/nouveau_drm.h __u32 tile_mode;