tgcr              200 arch/arm/mach-davinci/time.c 		u32 tgcr;
tgcr              210 arch/arm/mach-davinci/time.c 		tgcr = 0;
tgcr              211 arch/arm/mach-davinci/time.c 		__raw_writel(tgcr, base[i] + TGCR);
tgcr              214 arch/arm/mach-davinci/time.c 		tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
tgcr              215 arch/arm/mach-davinci/time.c 		__raw_writel(tgcr, base[i] + TGCR);
tgcr              218 arch/arm/mach-davinci/time.c 		tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
tgcr              220 arch/arm/mach-davinci/time.c 		__raw_writel(tgcr, base[i] + TGCR);
tgcr               28 arch/c6x/platforms/timer64.c 	u32	tgcr;
tgcr              104 arch/c6x/platforms/timer64.c 	val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
tgcr              105 arch/c6x/platforms/timer64.c 	soc_writel(val, &timer->tgcr);
tgcr              106 arch/c6x/platforms/timer64.c 	soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr);
tgcr              370 drivers/input/touchscreen/fsl-imx25-tcq.c 	u32 tgcr;
tgcr              378 drivers/input/touchscreen/fsl-imx25-tcq.c 	regmap_read(priv->core_regs, MX25_TSC_TGCR, &tgcr);
tgcr              379 drivers/input/touchscreen/fsl-imx25-tcq.c 	ipg_div = max_t(unsigned int, 4, MX25_TGCR_GET_ADCCLK(tgcr));
tgcr               72 drivers/watchdog/davinci_wdt.c 	u32 tgcr;
tgcr               83 drivers/watchdog/davinci_wdt.c 	tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
tgcr               84 drivers/watchdog/davinci_wdt.c 	iowrite32(tgcr, davinci_wdt->base + TGCR);
tgcr              146 drivers/watchdog/davinci_wdt.c 	u32 tgcr, wdtcr;
tgcr              152 drivers/watchdog/davinci_wdt.c 	tgcr = 0;
tgcr              153 drivers/watchdog/davinci_wdt.c 	iowrite32(tgcr, davinci_wdt->base + TGCR);
tgcr              154 drivers/watchdog/davinci_wdt.c 	tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
tgcr              155 drivers/watchdog/davinci_wdt.c 	iowrite32(tgcr, davinci_wdt->base + TGCR);