tg_mask            39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	optc1->tg_shift->field_name, optc1->tg_mask->field_name
tg_mask          1524 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
tg_mask          1525 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
tg_mask           503 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	const struct dcn_optc_mask *tg_mask;
tg_mask           433 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn_optc_mask tg_mask = {
tg_mask           731 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	tgn10->tg_mask = &tg_mask;
tg_mask            38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	optc1->tg_shift->field_name, optc1->tg_mask->field_name
tg_mask           478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
tg_mask           479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
tg_mask           776 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn_optc_mask tg_mask = {
tg_mask          1133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	tgn10->tg_mask = &tg_mask;
tg_mask           443 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn_optc_mask tg_mask = {
tg_mask          1223 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	tgn10->tg_mask = &tg_mask;
tg_mask            95 drivers/net/ethernet/mscc/ocelot_ace.c 	u32 tg_mask; /* Current type-group mask */
tg_mask           199 drivers/net/ethernet/mscc/ocelot_ace.c 	data->tg_mask = 0;
tg_mask           203 drivers/net/ethernet/mscc/ocelot_ace.c 		data->tg_mask |= GENMASK(offset + width - 1, offset);
tg_mask           348 drivers/net/ethernet/mscc/ocelot_ace.c 	data.tg = (data.tg & ~data.tg_mask);