tg_inst 976 drivers/gpu/drm/amd/display/dc/core/dc.c unsigned int enc_inst, tg_inst; tg_inst 997 drivers/gpu/drm/amd/display/dc/core/dc.c tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg( tg_inst 1000 drivers/gpu/drm/amd/display/dc/core/dc.c if (tg_inst >= dc->res_pool->timing_generator_count) tg_inst 1003 drivers/gpu/drm/amd/display/dc/core/dc.c tg = dc->res_pool->timing_generators[tg_inst]; tg_inst 1016 drivers/gpu/drm/amd/display/dc/core/dc.c tg_inst, &pix_clk_100hz); tg_inst 1857 drivers/gpu/drm/amd/display/dc/core/dc_resource.c unsigned int inst, tg_inst; tg_inst 1878 drivers/gpu/drm/amd/display/dc/core/dc_resource.c tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]); tg_inst 1880 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (tg_inst >= pool->timing_generator_count) tg_inst 1883 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (!res_ctx->pipe_ctx[tg_inst].stream) { tg_inst 1884 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; tg_inst 1886 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; tg_inst 1887 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.mi = pool->mis[tg_inst]; tg_inst 1888 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; tg_inst 1889 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; tg_inst 1890 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; tg_inst 1891 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; tg_inst 1892 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.opp = pool->opps[tg_inst]; tg_inst 1894 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pool->dpps[tg_inst]) tg_inst 1895 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; tg_inst 1896 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->pipe_idx = tg_inst; tg_inst 1899 drivers/gpu/drm/amd/display/dc/core/dc_resource.c return tg_inst; tg_inst 168 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c unsigned int tg_inst) tg_inst 171 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], tg_inst 177 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], tg_inst 181 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], tg_inst 187 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], tg_inst 191 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) tg_inst 192 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], tg_inst 196 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c clk_src->id, tg_inst); tg_inst 837 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h unsigned int tg_inst); tg_inst 1589 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c int tg_inst, bool enable) tg_inst 1592 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); tg_inst 1598 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c int tg_inst) tg_inst 1602 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); tg_inst 1608 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t tg_inst = 0; tg_inst 1611 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); tg_inst 1613 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c return tg_inst; tg_inst 1529 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c int tg_inst, bool enable) tg_inst 1532 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); tg_inst 1538 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c int tg_inst) tg_inst 1542 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); tg_inst 1548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t tg_inst = 0; tg_inst 1551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); tg_inst 1553 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c return tg_inst; tg_inst 567 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h int tg_inst, bool enable); tg_inst 599 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h int tg_inst); tg_inst 201 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h int tg_inst, tg_inst 209 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h int tg_inst);