tg110 425 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c struct dce110_timing_generator *tg110 = tg110 428 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (!tg110) tg110 431 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce110_timing_generator_construct(tg110, ctx, instance, offsets); tg110 432 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &tg110->base; tg110 466 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c struct dce110_timing_generator *tg110 = tg110 469 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!tg110) tg110 472 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce110_timing_generator_construct(tg110, ctx, instance, offsets); tg110 473 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &tg110->base; tg110 48 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c #define CRTC_REG(reg) (reg + tg110->offsets.crtc) tg110 49 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c #define DCP_REG(reg) (reg + tg110->offsets.dcp) tg110 97 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 110 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 127 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 146 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true); tg110 155 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 191 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 236 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 238 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false); tg110 260 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 288 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 308 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bp_params.controller_id = tg110->controller_id; tg110 347 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.funcs->enable_advanced_request(tg, true, &patched_crtc_timing); tg110 374 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 474 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 510 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 533 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 572 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 607 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 710 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1117 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1140 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->h_total > tg110->max_h_total || tg110 1141 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->v_total > tg110->max_v_total) tg110 1148 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (h_blank < tg110->min_h_blank) tg110 1151 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (timing->h_front_porch < tg110->min_h_front_porch) tg110 1159 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (h_back_porch < tg110->min_h_back_porch) tg110 1219 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1320 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1414 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1476 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1497 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1586 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1714 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1777 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1803 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1805 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c switch (tg110->controller_id) { tg110 1853 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1897 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1929 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1970 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1988 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 2051 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 2090 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 2105 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 2182 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 2245 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dce110_timing_generator *tg110, tg110 2250 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->controller_id = CONTROLLER_ID_D0 + instance; tg110 2251 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.inst = instance; tg110 2253 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->offsets = *offsets; tg110 2255 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.funcs = &dce110_tg_funcs; tg110 2257 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.ctx = ctx; tg110 2258 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.bp = ctx->dc_bios; tg110 2260 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1; tg110 2261 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1; tg110 2263 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->min_h_blank = 56; tg110 2264 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->min_h_front_porch = 4; tg110 2265 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->min_h_back_porch = 4; tg110 690 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c struct dce110_timing_generator *tg110, tg110 693 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->controller_id = CONTROLLER_ID_UNDERLAY0; tg110 695 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->base.funcs = &dce110_tg_v_funcs; tg110 697 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->base.ctx = ctx; tg110 698 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->base.bp = ctx->dc_bios; tg110 700 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1; tg110 701 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1; tg110 703 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->min_h_blank = 56; tg110 704 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->min_h_front_porch = 4; tg110 705 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->min_h_back_porch = 4; tg110 30 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h struct dce110_timing_generator *tg110, tg110 444 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c struct dce110_timing_generator *tg110 = tg110 447 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (!tg110) tg110 450 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce110_timing_generator_construct(tg110, ctx, instance, offsets); tg110 451 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &tg110->base; tg110 532 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c struct dce110_timing_generator *tg110 = tg110 535 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (!tg110) tg110 538 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce120_timing_generator_construct(tg110, ctx, instance, offsets); tg110 539 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &tg110->base; tg110 43 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__) tg110 46 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__) tg110 89 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 93 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 111 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 120 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c if (v_blank < tg110->min_v_blank || tg110 121 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->h_sync_width < tg110->min_h_sync_width || tg110 122 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c timing->v_sync_width < tg110->min_v_sync_width) tg110 139 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 151 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true); tg110 160 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 172 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 176 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 188 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 192 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 203 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 249 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 253 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 261 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0); tg110 285 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 308 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 315 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 353 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 373 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 377 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 391 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 393 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c switch (tg110->controller_id) { tg110 441 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 492 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 505 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 516 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 521 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc, tg110 531 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc, tg110 548 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 606 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 611 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 626 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 642 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 648 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 669 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 676 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 698 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc, tg110 705 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 717 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 721 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc, tg110 728 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 754 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 758 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 776 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 786 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc, 0); tg110 824 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 841 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 941 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, 0); tg110 980 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value); tg110 993 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value); tg110 1067 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, 0); tg110 1070 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0); tg110 1082 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, value); tg110 1083 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value); tg110 1084 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, value); tg110 1096 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1120 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1124 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 1134 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1142 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc, 0); tg110 1180 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 1184 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 1192 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 1197 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets.crtc); tg110 1241 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c struct dce110_timing_generator *tg110, tg110 1246 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->controller_id = CONTROLLER_ID_D0 + instance; tg110 1247 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->base.inst = instance; tg110 1249 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->offsets = *offsets; tg110 1251 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->base.funcs = &dce120_tg_funcs; tg110 1253 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->base.ctx = ctx; tg110 1254 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->base.bp = ctx->dc_bios; tg110 1256 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->max_h_total = CRTC0_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1; tg110 1257 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->max_v_total = CRTC0_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1; tg110 1261 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->min_h_blank = 32; tg110 1263 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->min_h_front_porch = 0; tg110 1264 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->min_h_back_porch = 0; tg110 1266 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->min_h_sync_width = 8; tg110 1267 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->min_v_sync_width = 1; tg110 1268 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->min_v_blank = 3; tg110 35 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h struct dce110_timing_generator *tg110, tg110 457 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c struct dce110_timing_generator *tg110 = tg110 460 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!tg110) tg110 463 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_timing_generator_construct(tg110, ctx, instance, offsets); tg110 464 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &tg110->base; tg110 83 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c #define CRTC_REG(reg) (reg + tg110->offsets.crtc) tg110 84 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c #define DCP_REG(reg) (reg + tg110->offsets.dcp) tg110 85 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c #define DMIF_REG(reg) (reg + tg110->offsets.dmif) tg110 128 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); tg110 225 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c struct dce110_timing_generator *tg110, tg110 230 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->controller_id = CONTROLLER_ID_D0 + instance; tg110 231 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->base.inst = instance; tg110 232 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->offsets = *offsets; tg110 233 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->derived_offsets = reg_offsets[instance]; tg110 235 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->base.funcs = &dce80_tg_funcs; tg110 237 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->base.ctx = ctx; tg110 238 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->base.bp = ctx->dc_bios; tg110 240 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1; tg110 241 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1; tg110 243 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->min_h_blank = 56; tg110 244 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->min_h_front_porch = 4; tg110 245 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->min_h_back_porch = 4;