tf_shift           49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_shift          566 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	const struct dcn_dpp_shift *tf_shift,
tf_shift          576 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	dpp->tf_shift = tf_shift;
tf_shift         1348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	const struct dcn_dpp_shift *tf_shift;
tf_shift         1511 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	const struct dcn_dpp_shift *tf_shift,
tf_shift           50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_shift          138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
tf_shift          140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
tf_shift          233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
tf_shift          235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
tf_shift          280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
tf_shift          282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
tf_shift          284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
tf_shift          286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
tf_shift          289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
tf_shift          291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
tf_shift          293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
tf_shift          295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
tf_shift          297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;
tf_shift          299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
tf_shift          307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;
tf_shift          309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
tf_shift          311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;
tf_shift          313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
tf_shift          316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B;
tf_shift          318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;
tf_shift          320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;
tf_shift          322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
tf_shift          324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B;
tf_shift          326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;
tf_shift          487 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
tf_shift          489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
tf_shift           50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_shift          385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 				dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
tf_shift          389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn_dpp_shift tf_shift = {
tf_shift          596 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		       &tf_regs[inst], &tf_shift, &tf_mask);
tf_shift           49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_shift          499 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	const struct dcn2_dpp_shift *tf_shift,
tf_shift          509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	dpp->tf_shift = tf_shift;
tf_shift          630 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	const struct dcn2_dpp_shift *tf_shift;
tf_shift          703 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	const struct dcn2_dpp_shift *tf_shift,
tf_shift           44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_shift          210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
tf_shift          212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
tf_shift          214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
tf_shift          216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
tf_shift          219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
tf_shift          221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
tf_shift          223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
tf_shift          225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
tf_shift          227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
tf_shift          229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
tf_shift          694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn2_dpp_shift tf_shift = {
tf_shift          983 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			&tf_regs[inst], &tf_shift, &tf_mask))
tf_shift          611 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn2_dpp_shift tf_shift = {
tf_shift          667 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			&tf_regs[inst], &tf_shift, &tf_mask))