tf_mask            49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_mask           510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
tf_mask           567 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	const struct dcn_dpp_mask *tf_mask)
tf_mask           577 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	dpp->tf_mask = tf_mask;
tf_mask          1349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	const struct dcn_dpp_mask *tf_mask;
tf_mask          1512 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	const struct dcn_dpp_mask *tf_mask);
tf_mask            50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_mask           139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.masks.csc_c11  = dpp->tf_mask->CM_GAMUT_REMAP_C11;
tf_mask           141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
tf_mask           234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.masks.csc_c11  = dpp->tf_mask->CM_OCSC_C11;
tf_mask           236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
tf_mask           281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
tf_mask           283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
tf_mask           285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
tf_mask           287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
tf_mask           290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
tf_mask           292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
tf_mask           294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
tf_mask           296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
tf_mask           298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;
tf_mask           300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
tf_mask           308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;
tf_mask           310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
tf_mask           312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;
tf_mask           314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
tf_mask           317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B;
tf_mask           319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;
tf_mask           321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;
tf_mask           323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
tf_mask           325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B;
tf_mask           327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;
tf_mask           488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.masks.csc_c11  = dpp->tf_mask->CM_ICSC_C11;
tf_mask           490 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
tf_mask           732 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	if (dpp->tf_mask->CM_BYPASS_EN)
tf_mask            50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_mask           384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 				scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
tf_mask           395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn_dpp_mask tf_mask = {
tf_mask           596 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		       &tf_regs[inst], &tf_shift, &tf_mask);
tf_mask            49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_mask           500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	const struct dcn2_dpp_mask *tf_mask)
tf_mask           510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	dpp->tf_mask = tf_mask;
tf_mask           631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	const struct dcn2_dpp_mask *tf_mask;
tf_mask           704 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	const struct dcn2_dpp_mask *tf_mask);
tf_mask            44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
tf_mask           211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
tf_mask           213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
tf_mask           215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
tf_mask           217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
tf_mask           220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
tf_mask           222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
tf_mask           224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
tf_mask           226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
tf_mask           228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
tf_mask           230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
tf_mask           698 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn2_dpp_mask tf_mask = {
tf_mask           983 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			&tf_regs[inst], &tf_shift, &tf_mask))
tf_mask           615 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn2_dpp_mask tf_mask = {
tf_mask           667 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			&tf_regs[inst], &tf_shift, &tf_mask))