temp_mpcc         194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		struct mpcc *temp_mpcc = tree->opp_list;
temp_mpcc         196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
temp_mpcc         197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			temp_mpcc = temp_mpcc->mpcc_bot;
temp_mpcc         198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		if (temp_mpcc == NULL)
temp_mpcc         226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		struct mpcc *temp_mpcc = tree->opp_list;
temp_mpcc         228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
temp_mpcc         229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			temp_mpcc = temp_mpcc->mpcc_bot;
temp_mpcc         230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) {
temp_mpcc         231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);
temp_mpcc         232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			temp_mpcc->mpcc_bot = new_mpcc;
temp_mpcc         234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
temp_mpcc         287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		struct mpcc *temp_mpcc = tree->opp_list;
temp_mpcc         289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove)
temp_mpcc         290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			temp_mpcc = temp_mpcc->mpcc_bot;
temp_mpcc         292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) {
temp_mpcc         294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot;
temp_mpcc         297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
temp_mpcc         301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
temp_mpcc         303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],