temp_cr 231 drivers/crypto/ux500/hash/hash_alg.h u32 temp_cr; temp_cr 1129 drivers/crypto/ux500/hash/hash_core.c u32 temp_cr; temp_cr 1154 drivers/crypto/ux500/hash/hash_core.c temp_cr = device_state->temp_cr; temp_cr 1155 drivers/crypto/ux500/hash/hash_core.c writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr); temp_cr 1174 drivers/crypto/ux500/hash/hash_core.c writel_relaxed(temp_cr, &device_data->base->cr); temp_cr 1187 drivers/crypto/ux500/hash/hash_core.c u32 temp_cr; temp_cr 1204 drivers/crypto/ux500/hash/hash_core.c temp_cr = readl_relaxed(&device_data->base->cr); temp_cr 1226 drivers/crypto/ux500/hash/hash_core.c device_state->temp_cr = temp_cr;