tc_enable 356 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c bool tc_enable = true; tc_enable 422 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos, tc_enable 434 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable); tc_enable 70 drivers/gpu/drm/zte/zx_vou.c u32 tc_enable; tc_enable 88 drivers/gpu/drm/zte/zx_vou.c .tc_enable = MAIN_TC_EN, tc_enable 106 drivers/gpu/drm/zte/zx_vou.c .tc_enable = AUX_TC_EN, tc_enable 425 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, tc_enable 426 drivers/gpu/drm/zte/zx_vou.c bits->tc_enable); tc_enable 472 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0);