tbl_A             128 drivers/phy/qualcomm/phy-qcom-ufs-i.h 			struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
tbl_A              14 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c 	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
tbl_A              23 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c 		tbl_A = phy_cal_table_rate_A_1_2_0;
tbl_A              26 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c 		tbl_A = phy_cal_table_rate_A_1_3_0;
tbl_A              37 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c 	err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
tbl_A              17 drivers/phy/qualcomm/phy-qcom-ufs.c 			   struct ufs_qcom_phy_calibration *tbl_A,
tbl_A              25 drivers/phy/qualcomm/phy-qcom-ufs.c 	if (!tbl_A) {
tbl_A              32 drivers/phy/qualcomm/phy-qcom-ufs.c 		writel_relaxed(tbl_A[i].cfg_value,
tbl_A              33 drivers/phy/qualcomm/phy-qcom-ufs.c 			       ufs_qcom_phy->mmio + tbl_A[i].reg_offset);