target_vco_rate   225 drivers/clk/analogbits/wrpll-cln28hpc.c 	u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre;
target_vco_rate   255 drivers/clk/analogbits/wrpll-cln28hpc.c 	divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
target_vco_rate   261 drivers/clk/analogbits/wrpll-cln28hpc.c 	ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
target_vco_rate   282 drivers/clk/analogbits/wrpll-cln28hpc.c 		if (vco > target_vco_rate) {