target_clock      122 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c 	unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?
target_clock      172 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c 		post_div_min = vco_min / target_clock;
target_clock      173 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c 		if ((target_clock * post_div_min) < vco_min)
target_clock      178 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c 		post_div_max = vco_max / target_clock;
target_clock      179 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c 		if ((target_clock * post_div_max) > vco_max)
target_clock      186 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c 	nom = target_clock;
target_clock      203 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c 		diff = abs(target_clock - (pll->reference_freq * fb_div) /
target_clock     9515 drivers/gpu/drm/i915/display/intel_display.c int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
target_clock     9522 drivers/gpu/drm/i915/display/intel_display.c 	u32 bps = target_clock * bpp * 21 / 20;
target_clock      462 drivers/gpu/drm/i915/display/intel_display.h int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
target_clock      596 drivers/gpu/drm/i915/display/intel_dp.c 	int target_clock = mode->clock;
target_clock      614 drivers/gpu/drm/i915/display/intel_dp.c 		target_clock = fixed_mode->clock;
target_clock      621 drivers/gpu/drm/i915/display/intel_dp.c 	mode_rate = intel_dp_link_required(target_clock, 18);
target_clock      639 drivers/gpu/drm/i915/display/intel_dp.c 							    target_clock,
target_clock      643 drivers/gpu/drm/i915/display/intel_dp.c 							     target_clock,
target_clock      649 drivers/gpu/drm/i915/display/intel_dp.c 	    target_clock > max_dotclk)
target_clock      227 drivers/gpu/drm/i915/display/intel_dvo.c 	int target_clock = mode->clock;
target_clock      240 drivers/gpu/drm/i915/display/intel_dvo.c 		target_clock = fixed_mode->clock;
target_clock      243 drivers/gpu/drm/i915/display/intel_dvo.c 	if (target_clock > max_dotclk)
target_clock      963 drivers/gpu/drm/radeon/radeon_display.c 	unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
target_clock     1016 drivers/gpu/drm/radeon/radeon_display.c 		post_div_min = vco_min / target_clock;
target_clock     1017 drivers/gpu/drm/radeon/radeon_display.c 		if ((target_clock * post_div_min) < vco_min)
target_clock     1022 drivers/gpu/drm/radeon/radeon_display.c 		post_div_max = vco_max / target_clock;
target_clock     1023 drivers/gpu/drm/radeon/radeon_display.c 		if ((target_clock * post_div_max) > vco_max)
target_clock     1030 drivers/gpu/drm/radeon/radeon_display.c 	nom = target_clock;
target_clock     1047 drivers/gpu/drm/radeon/radeon_display.c 		diff = abs(target_clock - (pll->reference_freq * fb_div) /