table_offset      297 arch/x86/pci/xen.c 			u32 table_offset, bir;
table_offset      301 arch/x86/pci/xen.c 					      &table_offset);
table_offset      302 arch/x86/pci/xen.c 			bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
table_offset       90 drivers/acpi/acpica/acapps.h acpi_status ac_validate_table_header(FILE * file, long table_offset);
table_offset     2384 drivers/acpi/nfit/core.c 	u64 line_no, table_skip_count, table_offset;
table_offset     2390 drivers/acpi/nfit/core.c 	table_offset = table_skip_count * mmio->table_size;
table_offset     2392 drivers/acpi/nfit/core.c 	return mmio->base_offset + line_offset + table_offset + sub_line_offset;
table_offset      641 drivers/acpi/tables.c 	int table_offset = 0;
table_offset      651 drivers/acpi/tables.c 	while (table_offset + ACPI_HEADER_SIZE <= all_tables_size) {
table_offset      652 drivers/acpi/tables.c 		table = acpi_os_map_memory(acpi_tables_addr + table_offset,
table_offset      654 drivers/acpi/tables.c 		if (table_offset + table->length > all_tables_size) {
table_offset      682 drivers/acpi/tables.c 		*address = acpi_tables_addr + table_offset;
table_offset      690 drivers/acpi/tables.c 		table_offset += table_length;
table_offset      698 drivers/acpi/tables.c 	int table_offset = 0;
table_offset      706 drivers/acpi/tables.c 	while (table_offset + ACPI_HEADER_SIZE <= all_tables_size) {
table_offset      707 drivers/acpi/tables.c 		table = acpi_os_map_memory(acpi_tables_addr + table_offset,
table_offset      709 drivers/acpi/tables.c 		if (table_offset + table->length > all_tables_size) {
table_offset      737 drivers/acpi/tables.c 		acpi_install_table(acpi_tables_addr + table_offset, TRUE);
table_offset      739 drivers/acpi/tables.c 		table_offset += table_length;
table_offset      198 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c 	u32 table_offset, table_size;
table_offset      211 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c 			table_offset = le32_to_cpu(hdr->jt_offset);
table_offset      219 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c 			table_offset = le32_to_cpu(hdr->jt_offset);
table_offset      227 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c 			table_offset = le32_to_cpu(hdr->jt_offset);
table_offset      235 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c 			table_offset = le32_to_cpu(hdr->jt_offset);
table_offset      243 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c 			table_offset = le32_to_cpu(hdr->jt_offset);
table_offset      249 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c 				cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
table_offset       75 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_table_offset(hwmgr,
table_offset       78 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0)
table_offset       79 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		return table_offset + 1;
table_offset       87 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
table_offset       91 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0) {
table_offset       93 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			(((unsigned long) powerplay_table) + table_offset);
table_offset      103 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
table_offset      106 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0)
table_offset      107 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		return table_offset + get_vce_clock_info_array_size(hwmgr,
table_offset      116 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
table_offset      119 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0) {
table_offset      121 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			(const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)(((unsigned long) powerplay_table) + table_offset);
table_offset      130 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
table_offset      132 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0)
table_offset      133 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table);
table_offset      142 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table);
table_offset      144 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0)
table_offset      145 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		return (const ATOM_PPLIB_VCE_State_Table *)(((unsigned long) powerplay_table) + table_offset);
table_offset      175 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_uvd_table_offset(hwmgr,
table_offset      178 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0)
table_offset      179 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		return table_offset + 1;
table_offset      186 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
table_offset      190 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0) {
table_offset      193 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 					+ table_offset);
table_offset      205 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
table_offset      208 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0)
table_offset      209 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		return table_offset +
table_offset      242 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_samu_table_offset(hwmgr,
table_offset      245 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0)
table_offset      246 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		return table_offset + 1;
table_offset     1237 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset;
table_offset     1253 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr,
table_offset     1255 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (vce_clock_info_array_offset > 0 && table_offset > 0) {
table_offset     1261 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				(((unsigned long) powerplay_table) + table_offset);
table_offset     1268 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_uvd_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
table_offset     1270 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (uvd_clock_info_array_offset > 0 && table_offset > 0) {
table_offset     1276 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				(((unsigned long) powerplay_table) + table_offset);
table_offset     1281 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr,
table_offset     1284 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0) {
table_offset     1287 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				(((unsigned long) powerplay_table) + table_offset);
table_offset     1292 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_acp_clock_voltage_limit_table_offset(hwmgr,
table_offset     1295 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0) {
table_offset     1298 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				(((unsigned long) powerplay_table) + table_offset);
table_offset     1303 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_cacp_tdp_table_offset(hwmgr, powerplay_table);
table_offset     1304 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0) {
table_offset     1305 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		UCHAR rev_id = *(UCHAR *)(((unsigned long)powerplay_table) + table_offset);
table_offset     1310 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				(((unsigned long) powerplay_table) + table_offset);
table_offset     1319 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				(((unsigned long) powerplay_table) + table_offset);
table_offset     1382 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(hwmgr,
table_offset     1385 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (table_offset > 0) {
table_offset     1387 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			(((unsigned long) powerplay_table) + table_offset);
table_offset     1471 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		uint16_t table_offset;
table_offset     1517 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				table_offset = le16_to_cpu(extended_header->usPPMTableOffset);
table_offset     1519 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 					(((unsigned long)powerplay_table) + table_offset);
table_offset     6430 drivers/gpu/drm/radeon/cik.c 	u32 table_offset, table_size;
table_offset     6449 drivers/gpu/drm/radeon/cik.c 				table_offset = le32_to_cpu(hdr->jt_offset);
table_offset     6455 drivers/gpu/drm/radeon/cik.c 				table_offset = le32_to_cpu(hdr->jt_offset);
table_offset     6461 drivers/gpu/drm/radeon/cik.c 				table_offset = le32_to_cpu(hdr->jt_offset);
table_offset     6467 drivers/gpu/drm/radeon/cik.c 				table_offset = le32_to_cpu(hdr->jt_offset);
table_offset     6473 drivers/gpu/drm/radeon/cik.c 				table_offset = le32_to_cpu(hdr->jt_offset);
table_offset     6479 drivers/gpu/drm/radeon/cik.c 					cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
table_offset     6488 drivers/gpu/drm/radeon/cik.c 				table_offset = CP_ME_TABLE_OFFSET;
table_offset     6491 drivers/gpu/drm/radeon/cik.c 				table_offset = CP_ME_TABLE_OFFSET;
table_offset     6494 drivers/gpu/drm/radeon/cik.c 				table_offset = CP_ME_TABLE_OFFSET;
table_offset     6497 drivers/gpu/drm/radeon/cik.c 				table_offset = CP_MEC_TABLE_OFFSET;
table_offset     6502 drivers/gpu/drm/radeon/cik.c 					cpu_to_le32(be32_to_cpu(fw_data[table_offset + i]));
table_offset     1504 drivers/net/ethernet/broadcom/b44.c static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
table_offset     1510 drivers/net/ethernet/broadcom/b44.c 		bw32(bp, B44_FILT_ADDR, table_offset + i);
table_offset      677 drivers/pci/msi.c 	u32 table_offset;
table_offset      682 drivers/pci/msi.c 			      &table_offset);
table_offset      683 drivers/pci/msi.c 	bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
table_offset      688 drivers/pci/msi.c 	table_offset &= PCI_MSIX_TABLE_OFFSET;
table_offset      689 drivers/pci/msi.c 	phys_addr = pci_resource_start(dev, bir) + table_offset;
table_offset     1005 tools/objtool/check.c 	unsigned long table_offset;
table_offset     1033 tools/objtool/check.c 		table_offset = text_rela->addend;
table_offset     1037 tools/objtool/check.c 			table_offset += 4;
table_offset     1048 tools/objtool/check.c 		if (find_symbol_containing(table_sec, table_offset) &&
table_offset     1053 tools/objtool/check.c 		table_rela = find_rela_by_dest(table_sec, table_offset);