t_ck               75 drivers/memory/emif.c static u32		t_ck; /* DDR clock period in ps */
t_ck              219 drivers/memory/emif.c 	t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
t_ck              437 drivers/memory/emif.c 	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
t_ck              441 drivers/memory/emif.c 		val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
t_ck              443 drivers/memory/emif.c 		val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
t_ck              446 drivers/memory/emif.c 	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
t_ck              449 drivers/memory/emif.c 	val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
t_ck              452 drivers/memory/emif.c 	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
t_ck              455 drivers/memory/emif.c 	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
t_ck              458 drivers/memory/emif.c 	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
t_ck              470 drivers/memory/emif.c 	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
t_ck              478 drivers/memory/emif.c 		val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
t_ck              480 drivers/memory/emif.c 		val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
t_ck              485 drivers/memory/emif.c 	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
t_ck              488 drivers/memory/emif.c 	val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
t_ck              492 drivers/memory/emif.c 	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
t_ck              495 drivers/memory/emif.c 	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
t_ck              498 drivers/memory/emif.c 	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
t_ck              514 drivers/memory/emif.c 	val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
t_ck              518 drivers/memory/emif.c 	val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
t_ck              524 drivers/memory/emif.c 	val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
t_ck              541 drivers/memory/emif.c 	val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
t_ck              547 drivers/memory/emif.c 		val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
t_ck              549 drivers/memory/emif.c 		val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
t_ck              553 drivers/memory/emif.c 	val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
t_ck              556 drivers/memory/emif.c 	val = DIV_ROUND_UP(timings->tCKESR, t_ck);
t_ck              643 drivers/memory/emif.c 		val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
t_ck              662 drivers/memory/emif.c 		val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
t_ck              677 drivers/memory/emif.c 	val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
t_ck              707 drivers/memory/emif.c 			t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
t_ck              717 drivers/memory/emif.c 		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
t_ck              728 drivers/memory/emif.c 		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
t_ck              739 drivers/memory/emif.c 		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);