tWHR_min          833 drivers/mtd/nand/raw/denali.c 	we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
tWHR_min         2356 drivers/mtd/nand/raw/marvell_nand.c 	nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
tWHR_min          537 drivers/mtd/nand/raw/mtk_nand.c 	tw2r = timings->tWHR_min / 1000;
tWHR_min           53 drivers/mtd/nand/raw/nand_timings.c 			.tWHR_min = 120000,
tWHR_min           95 drivers/mtd/nand/raw/nand_timings.c 			.tWHR_min = 80000,
tWHR_min          137 drivers/mtd/nand/raw/nand_timings.c 			.tWHR_min = 80000,
tWHR_min          179 drivers/mtd/nand/raw/nand_timings.c 			.tWHR_min = 80000,
tWHR_min          221 drivers/mtd/nand/raw/nand_timings.c 			.tWHR_min = 80000,
tWHR_min          263 drivers/mtd/nand/raw/nand_timings.c 			.tWHR_min = 80000,
tWHR_min         1573 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	if (sdrt->tWHR_min > tset_mem &&
tWHR_min         1574 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	    (thold_att < sdrt->tWHR_min - tset_mem))
tWHR_min         1575 drivers/mtd/nand/raw/stm32_fmc2_nand.c 		thold_att = sdrt->tWHR_min - tset_mem;
tWHR_min         1460 drivers/mtd/nand/raw/sunxi_nand.c 	if (timings->tWHR_min > (min_clk_period * 32))
tWHR_min         1461 drivers/mtd/nand/raw/sunxi_nand.c 		min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32);
tWHR_min         1493 drivers/mtd/nand/raw/sunxi_nand.c 	tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
tWHR_min          801 drivers/mtd/nand/raw/tegra_nand.c 	reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1));
tWHR_min          478 include/linux/mtd/rawnand.h 	u32 tWHR_min;