tWB_max          1379 drivers/mtd/nand/raw/atmel/nand-controller.c 	ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
tWB_max           673 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c 	busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps);
tWB_max          2366 drivers/mtd/nand/raw/marvell_nand.c 		nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns);
tWB_max          2368 drivers/mtd/nand/raw/marvell_nand.c 		nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max,
tWB_max          1116 drivers/mtd/nand/raw/meson_nand.c 	meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max),
tWB_max           680 drivers/mtd/nand/raw/nand_base.c 	ndelay(PSEC_TO_NSEC(timings->tWB_max));
tWB_max          1022 drivers/mtd/nand/raw/nand_base.c 		NAND_OP_ADDR(3, addrs, PSEC_TO_NSEC(sdr->tWB_max)),
tWB_max          1065 drivers/mtd/nand/raw/nand_base.c 		NAND_OP_CMD(NAND_CMD_READSTART, PSEC_TO_NSEC(sdr->tWB_max)),
tWB_max          1160 drivers/mtd/nand/raw/nand_base.c 			NAND_OP_ADDR(1, &page, PSEC_TO_NSEC(sdr->tWB_max)),
tWB_max          1300 drivers/mtd/nand/raw/nand_base.c 		NAND_OP_CMD(NAND_CMD_PAGEPROG, PSEC_TO_NSEC(sdr->tWB_max)),
tWB_max          1414 drivers/mtd/nand/raw/nand_base.c 				    PSEC_TO_NSEC(sdr->tWB_max)),
tWB_max          1687 drivers/mtd/nand/raw/nand_base.c 				    PSEC_TO_MSEC(sdr->tWB_max)),
tWB_max          1745 drivers/mtd/nand/raw/nand_base.c 					      PSEC_TO_NSEC(sdr->tWB_max)),
tWB_max          1790 drivers/mtd/nand/raw/nand_base.c 			NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tWB_max)),
tWB_max          1846 drivers/mtd/nand/raw/nand_base.c 			NAND_OP_CMD(NAND_CMD_RESET, PSEC_TO_NSEC(sdr->tWB_max)),
tWB_max            50 drivers/mtd/nand/raw/nand_timings.c 			.tWB_max = 200000,
tWB_max            92 drivers/mtd/nand/raw/nand_timings.c 			.tWB_max = 100000,
tWB_max           133 drivers/mtd/nand/raw/nand_timings.c 			.tWB_max = 100000,
tWB_max           176 drivers/mtd/nand/raw/nand_timings.c 			.tWB_max = 100000,
tWB_max           218 drivers/mtd/nand/raw/nand_timings.c 			.tWB_max = 100000,
tWB_max           260 drivers/mtd/nand/raw/nand_timings.c 			.tWB_max = 100000,
tWB_max          1348 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	ndelay(PSEC_TO_NSEC(timings->tWB_max));
tWB_max          1564 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
tWB_max          1565 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	    (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
tWB_max          1566 drivers/mtd/nand/raw/stm32_fmc2_nand.c 		thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
tWB_max          1454 drivers/mtd/nand/raw/sunxi_nand.c 	if (timings->tWB_max > (min_clk_period * 20))
tWB_max          1455 drivers/mtd/nand/raw/sunxi_nand.c 		min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20);
tWB_max          1480 drivers/mtd/nand/raw/sunxi_nand.c 	tWB  = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
tWB_max           495 drivers/mtd/nand/raw/tango_nand.c 	Textw = to_ticks(kHz, sdr->tWB_max);
tWB_max           800 drivers/mtd/nand/raw/tegra_nand.c 	reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1));
tWB_max           475 include/linux/mtd/rawnand.h 	u32 tWB_max;