tRR_min          1372 drivers/mtd/nand/raw/atmel/nand-controller.c 	ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
tRR_min          1192 drivers/mtd/nand/raw/mxc_nand.c 	    timings->tRR_min > 6 * tRC_ps ||
tRR_min          1024 drivers/mtd/nand/raw/nand_base.c 				 PSEC_TO_NSEC(sdr->tRR_min)),
tRR_min          1067 drivers/mtd/nand/raw/nand_base.c 				 PSEC_TO_NSEC(sdr->tRR_min)),
tRR_min          1162 drivers/mtd/nand/raw/nand_base.c 					 PSEC_TO_NSEC(sdr->tRR_min)),
tRR_min          1792 drivers/mtd/nand/raw/nand_base.c 					 PSEC_TO_NSEC(sdr->tRR_min)),
tRR_min            48 drivers/mtd/nand/raw/nand_timings.c 			.tRR_min = 40000,
tRR_min            90 drivers/mtd/nand/raw/nand_timings.c 			.tRR_min = 20000,
tRR_min           131 drivers/mtd/nand/raw/nand_timings.c 			.tRR_min = 20000,
tRR_min           174 drivers/mtd/nand/raw/nand_timings.c 			.tRR_min = 20000,
tRR_min           216 drivers/mtd/nand/raw/nand_timings.c 			.tRR_min = 20000,
tRR_min           258 drivers/mtd/nand/raw/nand_timings.c 			.tRR_min = 20000,
tRR_min          1430 drivers/mtd/nand/raw/sunxi_nand.c 	if (timings->tRR_min > (min_clk_period * 3))
tRR_min          1431 drivers/mtd/nand/raw/sunxi_nand.c 		min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
tRR_min           787 drivers/mtd/nand/raw/tegra_nand.c 	val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min,
tRR_min           473 include/linux/mtd/rawnand.h 	u32 tRR_min;