t11_t12 2097 drivers/gpu/drm/gma500/cdv_intel_dp.c cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> t11_t12 2101 drivers/gpu/drm/gma500/cdv_intel_dp.c cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); t11_t12 2108 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100; t11_t12 85 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.pps.t11_t12); t11_t12 449 drivers/gpu/drm/gma500/intel_bios.h u16 t11_t12; t11_t12 53 drivers/gpu/drm/i915/display/intel_bios.h u16 t11_t12; t11_t12 6406 drivers/gpu/drm/i915/display/intel_dp.c seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; t11_t12 6408 drivers/gpu/drm/i915/display/intel_dp.c seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; t11_t12 6417 drivers/gpu/drm/i915/display/intel_dp.c seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); t11_t12 6429 drivers/gpu/drm/i915/display/intel_dp.c hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { t11_t12 6446 drivers/gpu/drm/i915/display/intel_dp.c if (final->t11_t12 != 0) t11_t12 6460 drivers/gpu/drm/i915/display/intel_dp.c vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); t11_t12 6462 drivers/gpu/drm/i915/display/intel_dp.c vbt.t11_t12); t11_t12 6468 drivers/gpu/drm/i915/display/intel_dp.c vbt.t11_t12 += 100 * 10; t11_t12 6480 drivers/gpu/drm/i915/display/intel_dp.c spec.t11_t12 = (510 + 100) * 10; t11_t12 6493 drivers/gpu/drm/i915/display/intel_dp.c assign_final(t11_t12); t11_t12 6501 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->panel_power_cycle_delay = get_delay(t11_t12); t11_t12 6525 drivers/gpu/drm/i915/display/intel_dp.c final->t11_t12 = roundup(final->t11_t12, 100 * 10); t11_t12 6605 drivers/gpu/drm/i915/display/intel_dp.c REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); t11_t12 6611 drivers/gpu/drm/i915/display/intel_dp.c pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));