sysram_ns_base_addr   92 arch/arm/mach-exynos/common.h extern void __iomem *sysram_ns_base_addr;
sysram_ns_base_addr   37 arch/arm/mach-exynos/exynos.c void __iomem *sysram_ns_base_addr __ro_after_init;
sysram_ns_base_addr   55 arch/arm/mach-exynos/exynos.c 		sysram_ns_base_addr = of_iomap(node, 0);
sysram_ns_base_addr   41 arch/arm/mach-exynos/firmware.c 			       sysram_ns_base_addr + 0x24);
sysram_ns_base_addr   42 arch/arm/mach-exynos/firmware.c 		writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
sysram_ns_base_addr   78 arch/arm/mach-exynos/firmware.c 	if (!sysram_ns_base_addr)
sysram_ns_base_addr   81 arch/arm/mach-exynos/firmware.c 	boot_reg = sysram_ns_base_addr + 0x1c;
sysram_ns_base_addr   99 arch/arm/mach-exynos/firmware.c 	if (!sysram_ns_base_addr)
sysram_ns_base_addr  102 arch/arm/mach-exynos/firmware.c 	boot_reg = sysram_ns_base_addr + 0x1c;
sysram_ns_base_addr  119 arch/arm/mach-exynos/firmware.c 	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
sysram_ns_base_addr  128 arch/arm/mach-exynos/firmware.c 	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
sysram_ns_base_addr  130 arch/arm/mach-exynos/firmware.c 		sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
sysram_ns_base_addr  137 arch/arm/mach-exynos/firmware.c 	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
sysram_ns_base_addr  230 arch/arm/mach-exynos/firmware.c #define REG_CPU_STATE_ADDR	(sysram_ns_base_addr + 0x28)
sysram_ns_base_addr  696 arch/arm/mach-exynos/suspend.c 		pm_state.sysram_base = sysram_ns_base_addr;