sys_offset 15 arch/alpha/include/asm/mce.h unsigned int sys_offset; /* system-specific offset */ sys_offset 406 arch/alpha/kernel/core_apecs.c (la_ptr + mchk_header->sys_offset); sys_offset 1113 arch/alpha/kernel/core_cia.c cia = (void *)(la_ptr + com->sys_offset); sys_offset 549 arch/alpha/kernel/core_mcpcia.c iodpp = (struct IOD_subpacket *) (la_ptr + frame->sys_offset); sys_offset 65 arch/alpha/kernel/err_common.c mchk_header->sys_offset); sys_offset 69 arch/alpha/kernel/err_common.c mchk_header->sys_offset - mchk_header->proc_offset, sys_offset 74 arch/alpha/kernel/err_common.c ((unsigned long)mchk_header + mchk_header->sys_offset), sys_offset 75 arch/alpha/kernel/err_common.c mchk_header->size - mchk_header->sys_offset, sys_offset 374 arch/alpha/kernel/err_titan.c ((unsigned long)mchk_header + mchk_header->sys_offset); sys_offset 394 arch/alpha/kernel/err_titan.c ((unsigned long)mchk_header + mchk_header->sys_offset); sys_offset 596 arch/alpha/kernel/err_titan.c ((unsigned long)mchk_header + mchk_header->sys_offset); sys_offset 714 arch/alpha/kernel/err_titan.c (la_ptr + mchk_header->sys_offset); sys_offset 164 drivers/gpu/drm/mediatek/mtk_hdmi.c unsigned int sys_offset; sys_offset 242 drivers/gpu/drm/mediatek/mtk_hdmi.c hdmi->sys_offset + HDMI_SYS_CFG20, sys_offset 248 drivers/gpu/drm/mediatek/mtk_hdmi.c regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, sys_offset 250 drivers/gpu/drm/mediatek/mtk_hdmi.c regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, sys_offset 256 drivers/gpu/drm/mediatek/mtk_hdmi.c regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, sys_offset 272 drivers/gpu/drm/mediatek/mtk_hdmi.c regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, sys_offset 274 drivers/gpu/drm/mediatek/mtk_hdmi.c regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, sys_offset 277 drivers/gpu/drm/mediatek/mtk_hdmi.c regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, sys_offset 364 drivers/gpu/drm/mediatek/mtk_hdmi.c regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, sys_offset 367 drivers/gpu/drm/mediatek/mtk_hdmi.c regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, sys_offset 373 drivers/gpu/drm/mediatek/mtk_hdmi.c regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, sys_offset 1478 drivers/gpu/drm/mediatek/mtk_hdmi.c &hdmi->sys_offset);