swizzle            29 arch/arm/include/asm/mach/pci.h 	u8		(*swizzle)(struct pci_dev *dev, u8 *pin);
swizzle            51 arch/arm/include/asm/mach/pci.h 	u8		(*swizzle)(struct pci_dev *, u8 *);
swizzle           384 arch/arm/kernel/bios32.c 	if (sys->swizzle)
swizzle           385 arch/arm/kernel/bios32.c 		slot = sys->swizzle(dev, pin);
swizzle           471 arch/arm/kernel/bios32.c 		sys->swizzle = hw->swizzle;
swizzle            48 arch/arm/mach-footbridge/cats-pci.c 	.swizzle		= cats_no_swizzle,
swizzle          2734 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	input.swizzle_mode = tiling_info->gfx9.swizzle;
swizzle          2876 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		tiling_info->gfx9.swizzle =
swizzle           334 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
swizzle           343 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
swizzle           982 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					pipe->plane_state->tiling_info.gfx9.swizzle);
swizzle          1452 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
swizzle           171 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx9.swizzle);
swizzle           257 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 					update->plane_info->tiling_info.gfx9.swizzle);
swizzle          2062 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
swizzle           380 drivers/gpu/drm/amd/display/dc/dc_hw_types.h 		enum swizzle_mode_values swizzle;
swizzle           360 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 				GRPH_SW_MODE, info->gfx9.swizzle,
swizzle           724 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		enum swizzle_mode_values swizzle,
swizzle           732 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	switch (swizzle) {
swizzle           157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			SW_MODE, info->gfx9.swizzle,
swizzle          1204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	enum swizzle_mode_values swizzle = DC_SW_LINEAR;
swizzle          1207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		swizzle = DC_SW_64KB_D;
swizzle          1209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		swizzle = DC_SW_64KB_S;
swizzle          1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	plane_state->tiling_info.gfx9.swizzle = swizzle;
swizzle            57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		enum swizzle_mode_values swizzle,
swizzle            66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	switch (swizzle) {
swizzle            93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h 		enum swizzle_mode_values swizzle,
swizzle           316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 			SW_MODE, info->gfx9.swizzle,
swizzle          1663 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		enum swizzle_mode_values swizzle,
swizzle          1666 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	switch (swizzle) {
swizzle          2130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
swizzle          2131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
swizzle          2993 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	enum swizzle_mode_values swizzle = DC_SW_LINEAR;
swizzle          2996 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		swizzle = DC_SW_64KB_D;
swizzle          2998 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		swizzle = DC_SW_64KB_S;
swizzle          3000 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	plane_state->tiling_info.gfx9.swizzle = swizzle;
swizzle           125 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h 			enum swizzle_mode_values swizzle,
swizzle            21 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	unsigned int swizzle;
swizzle            59 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	switch (tile->swizzle) {
swizzle           219 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		tile.swizzle = I915_BIT_6_SWIZZLE_NONE;
swizzle           244 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 			tile.swizzle = i915->mm.bit_6_swizzle_x;
swizzle           247 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 			tile.swizzle = i915->mm.bit_6_swizzle_y;
swizzle           251 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		GEM_BUG_ON(tile.swizzle == I915_BIT_6_SWIZZLE_UNKNOWN);
swizzle           252 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 ||
swizzle           253 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		    tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
swizzle          1624 drivers/gpu/drm/i915/i915_debugfs.c static const char *swizzle_string(unsigned swizzle)
swizzle          1626 drivers/gpu/drm/i915/i915_debugfs.c 	switch (swizzle) {