CM_BLNDGAM_LUT_WRITE_EN_MASK  797 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	type CM_BLNDGAM_LUT_WRITE_EN_MASK; \
CM_BLNDGAM_LUT_WRITE_EN_MASK 1169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \
CM_BLNDGAM_LUT_WRITE_EN_MASK   35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \
CM_BLNDGAM_LUT_WRITE_EN_MASK  344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \
CM_BLNDGAM_LUT_WRITE_EN_MASK  175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK,
CM_BLNDGAM_LUT_WRITE_EN_MASK  176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 			CM_BLNDGAM_LUT_WRITE_EN_MASK, 7);
CM_BLNDGAM_LUT_WRITE_EN_MASK  177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK,
CM_BLNDGAM_LUT_WRITE_EN_MASK  295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK,