swath_height_c   1156 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->swath_height_c[k] = v->maximum_swath_height_c;
swath_height_c   1160 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->swath_height_c[k] = v->minimum_swath_height_c;
swath_height_c   1162 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if (v->swath_height_c[k] == 0.0) {
swath_height_c   1166 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		else if (v->swath_height_y[k] <= v->swath_height_c[k]) {
swath_height_c   1314 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0 * v->swath_height_c[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth);
swath_height_c   1347 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->lines_in_detc_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]);
swath_height_c   1426 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]);
swath_height_c   1608 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->max_num_swath_c[k] =dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k], 1.0) + 1;
swath_height_c   1610 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 				v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0), v->swath_height_c[k]);
swath_height_c   1613 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 				v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0), v->swath_height_c[k]);
swath_height_c   1621 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k] + v->max_partial_swath_c;
swath_height_c   1730 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 					if ((v->swath_height_c[k] > 4.0)) {
swath_height_c   1732 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 							v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0) / 2.0));
swath_height_c   1856 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->max_det_buffering_time_c = v->full_det_buffering_time_c[k] + (v->lines_in_detc[k] - v->lines_in_detc_rounded_down_to_swath[k]) / v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
swath_height_c   1859 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 				v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
swath_height_c   1038 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	unsigned int swath_height_c;
swath_height_c   1219 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	swath_height_c = rq_dlg_param.rq_c.swath_height;
swath_height_c   1314 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		DTRACE("DLG: %s: swath_height_c     = %d", __func__, swath_height_c);
swath_height_c   1361 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 				swath_height_c,
swath_height_c   1365 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	lsw_c = max_num_sw_c * swath_height_c + max_partial_sw_c;
swath_height_c   1497 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 				swath_height_c,
swath_height_c    225 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h 	float swath_height_c[number_of_planes_minus_one + 1];