sw_mode            50 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 			     bool sw_mode);
sw_mode           603 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 			     bool sw_mode)
sw_mode           615 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 	if (sw_mode) {
sw_mode           165 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
sw_mode           167 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	switch (sw_mode) {
sw_mode           256 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
sw_mode           258 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	switch (sw_mode) {
sw_mode           334 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
sw_mode           999 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			SW_MODE, &s->sw_mode);
sw_mode           642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	uint32_t sw_mode;
sw_mode           151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					s->sw_mode,
sw_mode           151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 					s->sw_mode,
sw_mode           171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 					s->sw_mode,
sw_mode          1197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 			SW_MODE, &s->sw_mode);
sw_mode          1664 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		unsigned int *sw_mode)
sw_mode          1668 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_linear;
sw_mode          1671 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_4kb_s;
sw_mode          1674 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_4kb_s_x;
sw_mode          1677 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_4kb_d;
sw_mode          1680 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_4kb_d_x;
sw_mode          1683 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_64kb_s;
sw_mode          1686 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_64kb_s_x;
sw_mode          1689 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_64kb_s_t;
sw_mode          1692 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_64kb_d;
sw_mode          1695 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_64kb_d_x;
sw_mode          1698 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_64kb_d_t;
sw_mode          1701 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_64kb_r_x;
sw_mode          1704 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_var_s;
sw_mode          1707 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_var_s_x;
sw_mode          1710 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_var_d;
sw_mode          1713 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		*sw_mode = dm_sw_var_d_x;
sw_mode          2046 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
sw_mode          2132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					&pipes[pipe_cnt].pipe.src.sw_mode);
sw_mode           245 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
sw_mode           714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			pipe_src_param.sw_mode,
sw_mode           245 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
sw_mode           714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			pipe_src_param.sw_mode,
sw_mode           228 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
sw_mode           755 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			pipe_param.src.sw_mode,
sw_mode           226 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	int sw_mode;
sw_mode           430 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 				(enum dm_swizzle_mode) (src->sw_mode);
sw_mode           284 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
sw_mode           630 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
sw_mode           667 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	if (pipe_src_param.sw_mode != dm_sw_linear)
sw_mode           916 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			pipe_src_param.sw_mode,
sw_mode           635 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode);
sw_mode          5172 drivers/gpu/drm/radeon/si.c 			   bool sw_mode)
sw_mode          5180 drivers/gpu/drm/radeon/si.c 	if (sw_mode) {
sw_mode            66 drivers/spi/spi-dw-mmio.c 		u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
sw_mode            69 drivers/spi/spi-dw-mmio.c 			sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
sw_mode            71 drivers/spi/spi-dw-mmio.c 		writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);