surf 534 drivers/gpu/drm/gma500/cdv_device.c .surf = DSPASURF, surf 559 drivers/gpu/drm/gma500/cdv_device.c .surf = DSPBSURF, surf 121 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->surf, start); surf 122 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->surf); surf 202 drivers/gpu/drm/gma500/mdfld_device.c pipe->surf = PSB_RVDC32(map->surf); surf 331 drivers/gpu/drm/gma500/mdfld_device.c PSB_WVDC32(pipe->surf, map->surf); surf 454 drivers/gpu/drm/gma500/mdfld_device.c .surf = DSPASURF, surf 476 drivers/gpu/drm/gma500/mdfld_device.c .surf = DSPBSURF, surf 499 drivers/gpu/drm/gma500/mdfld_device.c .surf = DSPCSURF, surf 633 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c pkg_sender->dspsurf_reg = map->surf; surf 217 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->surf, start); surf 218 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->surf); surf 642 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE(map->surf, start); surf 643 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ(map->surf); surf 213 drivers/gpu/drm/gma500/oaktrail_device.c p->surf = PSB_RVDC32(DSPASURF); surf 346 drivers/gpu/drm/gma500/oaktrail_device.c PSB_WVDC32(p->surf, DSPASURF); surf 470 drivers/gpu/drm/gma500/oaktrail_device.c .surf = DSPASURF, surf 494 drivers/gpu/drm/gma500/oaktrail_device.c .surf = DSPBSURF, surf 791 drivers/gpu/drm/gma500/oaktrail_hdmi.c pipeb->surf = PSB_RVDC32(DSPBSURF); surf 847 drivers/gpu/drm/gma500/oaktrail_hdmi.c PSB_WVDC32(pipeb->surf, DSPBSURF); surf 268 drivers/gpu/drm/gma500/psb_device.c .surf = DSPASURF, surf 292 drivers/gpu/drm/gma500/psb_device.c .surf = DSPBSURF, surf 281 drivers/gpu/drm/gma500/psb_drv.h u32 surf; surf 316 drivers/gpu/drm/gma500/psb_drv.h u32 surf; surf 332 drivers/gpu/drm/qxl/qxl_cmd.c int qxl_io_update_area(struct qxl_device *qdev, struct qxl_bo *surf, surf 339 drivers/gpu/drm/qxl/qxl_cmd.c if (!surf->hw_surf_alloc) surf 342 drivers/gpu/drm/qxl/qxl_cmd.c if (surf->is_primary) surf 345 drivers/gpu/drm/qxl/qxl_cmd.c surface_id = surf->surface_id; surf 346 drivers/gpu/drm/qxl/qxl_cmd.c surface_width = surf->surf.width; surf 347 drivers/gpu/drm/qxl/qxl_cmd.c surface_height = surf->surf.height; surf 393 drivers/gpu/drm/qxl/qxl_cmd.c create->format = bo->surf.format; surf 394 drivers/gpu/drm/qxl/qxl_cmd.c create->width = bo->surf.width; surf 395 drivers/gpu/drm/qxl/qxl_cmd.c create->height = bo->surf.height; surf 396 drivers/gpu/drm/qxl/qxl_cmd.c create->stride = bo->surf.stride; surf 427 drivers/gpu/drm/qxl/qxl_cmd.c struct qxl_bo *surf) surf 450 drivers/gpu/drm/qxl/qxl_cmd.c surf->surface_id = handle; surf 467 drivers/gpu/drm/qxl/qxl_cmd.c struct qxl_bo *surf) surf 473 drivers/gpu/drm/qxl/qxl_cmd.c if (surf->hw_surf_alloc) surf 490 drivers/gpu/drm/qxl/qxl_cmd.c cmd->u.surface_create.format = surf->surf.format; surf 491 drivers/gpu/drm/qxl/qxl_cmd.c cmd->u.surface_create.width = surf->surf.width; surf 492 drivers/gpu/drm/qxl/qxl_cmd.c cmd->u.surface_create.height = surf->surf.height; surf 493 drivers/gpu/drm/qxl/qxl_cmd.c cmd->u.surface_create.stride = surf->surf.stride; surf 494 drivers/gpu/drm/qxl/qxl_cmd.c cmd->u.surface_create.data = qxl_bo_physical_address(qdev, surf, 0); surf 495 drivers/gpu/drm/qxl/qxl_cmd.c cmd->surface_id = surf->surface_id; surf 498 drivers/gpu/drm/qxl/qxl_cmd.c surf->surf_create = release; surf 506 drivers/gpu/drm/qxl/qxl_cmd.c surf->hw_surf_alloc = true; surf 508 drivers/gpu/drm/qxl/qxl_cmd.c idr_replace(&qdev->surf_id_idr, surf, surf->surface_id); surf 514 drivers/gpu/drm/qxl/qxl_cmd.c struct qxl_bo *surf) surf 521 drivers/gpu/drm/qxl/qxl_cmd.c if (!surf->hw_surf_alloc) surf 525 drivers/gpu/drm/qxl/qxl_cmd.c surf->surf_create, surf 530 drivers/gpu/drm/qxl/qxl_cmd.c surf->surf_create = NULL; surf 533 drivers/gpu/drm/qxl/qxl_cmd.c idr_replace(&qdev->surf_id_idr, NULL, surf->surface_id); surf 535 drivers/gpu/drm/qxl/qxl_cmd.c surf->hw_surf_alloc = false; surf 537 drivers/gpu/drm/qxl/qxl_cmd.c id = surf->surface_id; surf 538 drivers/gpu/drm/qxl/qxl_cmd.c surf->surface_id = 0; surf 552 drivers/gpu/drm/qxl/qxl_cmd.c static int qxl_update_surface(struct qxl_device *qdev, struct qxl_bo *surf) surf 560 drivers/gpu/drm/qxl/qxl_cmd.c rect.right = surf->surf.width; surf 562 drivers/gpu/drm/qxl/qxl_cmd.c rect.bottom = surf->surf.height; surf 564 drivers/gpu/drm/qxl/qxl_cmd.c ret = qxl_io_update_area(qdev, surf, &rect); surf 570 drivers/gpu/drm/qxl/qxl_cmd.c static void qxl_surface_evict_locked(struct qxl_device *qdev, struct qxl_bo *surf, bool do_update_area) surf 574 drivers/gpu/drm/qxl/qxl_cmd.c qxl_update_surface(qdev, surf); surf 577 drivers/gpu/drm/qxl/qxl_cmd.c qxl_hw_surface_dealloc(qdev, surf); surf 580 drivers/gpu/drm/qxl/qxl_cmd.c void qxl_surface_evict(struct qxl_device *qdev, struct qxl_bo *surf, bool do_update_area) surf 583 drivers/gpu/drm/qxl/qxl_cmd.c qxl_surface_evict_locked(qdev, surf, do_update_area); surf 587 drivers/gpu/drm/qxl/qxl_cmd.c static int qxl_reap_surf(struct qxl_device *qdev, struct qxl_bo *surf, bool stall) surf 591 drivers/gpu/drm/qxl/qxl_cmd.c ret = qxl_bo_reserve(surf, false); surf 598 drivers/gpu/drm/qxl/qxl_cmd.c ret = ttm_bo_wait(&surf->tbo, true, !stall); surf 603 drivers/gpu/drm/qxl/qxl_cmd.c qxl_bo_unreserve(surf); surf 607 drivers/gpu/drm/qxl/qxl_cmd.c qxl_surface_evict_locked(qdev, surf, true); surf 608 drivers/gpu/drm/qxl/qxl_cmd.c qxl_bo_unreserve(surf); surf 215 drivers/gpu/drm/qxl/qxl_display.c return qxl_check_mode(qdev, bo->surf.width, bo->surf.height); surf 729 drivers/gpu/drm/qxl/qxl_display.c width = bo->surf.width; surf 730 drivers/gpu/drm/qxl/qxl_display.c height = bo->surf.height; surf 749 drivers/gpu/drm/qxl/qxl_display.c struct qxl_surface *surf) surf 754 drivers/gpu/drm/qxl/qxl_display.c memset(surf, 0, sizeof(*surf)); surf 757 drivers/gpu/drm/qxl/qxl_display.c head->x = surf->width; surf 758 drivers/gpu/drm/qxl/qxl_display.c surf->width += head->width; surf 759 drivers/gpu/drm/qxl/qxl_display.c if (surf->height < head->height) surf 760 drivers/gpu/drm/qxl/qxl_display.c surf->height = head->height; surf 762 drivers/gpu/drm/qxl/qxl_display.c if (surf->width < 64) surf 763 drivers/gpu/drm/qxl/qxl_display.c surf->width = 64; surf 764 drivers/gpu/drm/qxl/qxl_display.c if (surf->height < 64) surf 765 drivers/gpu/drm/qxl/qxl_display.c surf->height = 64; surf 766 drivers/gpu/drm/qxl/qxl_display.c surf->format = SPICE_SURFACE_FMT_32_xRGB; surf 767 drivers/gpu/drm/qxl/qxl_display.c surf->stride = surf->width * 4; surf 770 drivers/gpu/drm/qxl/qxl_display.c qdev->dumb_shadow_bo->surf.width != surf->width || surf 771 drivers/gpu/drm/qxl/qxl_display.c qdev->dumb_shadow_bo->surf.height != surf->height) surf 772 drivers/gpu/drm/qxl/qxl_display.c DRM_DEBUG("%dx%d\n", surf->width, surf->height); surf 781 drivers/gpu/drm/qxl/qxl_display.c struct qxl_surface surf; surf 794 drivers/gpu/drm/qxl/qxl_display.c qxl_calc_dumb_shadow(qdev, &surf); surf 796 drivers/gpu/drm/qxl/qxl_display.c qdev->dumb_shadow_bo->surf.width != surf.width || surf 797 drivers/gpu/drm/qxl/qxl_display.c qdev->dumb_shadow_bo->surf.height != surf.height) { surf 803 drivers/gpu/drm/qxl/qxl_display.c qxl_bo_create(qdev, surf.height * surf.stride, surf 804 drivers/gpu/drm/qxl/qxl_display.c true, true, QXL_GEM_DOMAIN_SURFACE, &surf, surf 92 drivers/gpu/drm/qxl/qxl_drv.h struct qxl_surface surf; surf 330 drivers/gpu/drm/qxl/qxl_drv.h struct qxl_surface *surf, surf 336 drivers/gpu/drm/qxl/qxl_drv.h struct qxl_surface *surf, surf 384 drivers/gpu/drm/qxl/qxl_drv.h int qxl_io_update_area(struct qxl_device *qdev, struct qxl_bo *surf, surf 467 drivers/gpu/drm/qxl/qxl_drv.h struct qxl_bo *surf); surf 471 drivers/gpu/drm/qxl/qxl_drv.h struct qxl_bo *surf); surf 473 drivers/gpu/drm/qxl/qxl_drv.h struct qxl_bo *surf); surf 479 drivers/gpu/drm/qxl/qxl_drv.h void qxl_surface_evict(struct qxl_device *qdev, struct qxl_bo *surf, bool freeing); surf 39 drivers/gpu/drm/qxl/qxl_dumb.c struct qxl_surface surf; surf 57 drivers/gpu/drm/qxl/qxl_dumb.c surf.width = args->width; surf 58 drivers/gpu/drm/qxl/qxl_dumb.c surf.height = args->height; surf 59 drivers/gpu/drm/qxl/qxl_dumb.c surf.stride = pitch; surf 60 drivers/gpu/drm/qxl/qxl_dumb.c surf.format = format; surf 63 drivers/gpu/drm/qxl/qxl_dumb.c args->size, &surf, &qobj, surf 48 drivers/gpu/drm/qxl/qxl_gem.c struct qxl_surface *surf, surf 58 drivers/gpu/drm/qxl/qxl_gem.c r = qxl_bo_create(qdev, size, kernel, false, initial_domain, surf, &qbo); surf 79 drivers/gpu/drm/qxl/qxl_gem.c struct qxl_surface *surf, surf 91 drivers/gpu/drm/qxl/qxl_gem.c false, false, surf, surf 400 drivers/gpu/drm/qxl/qxl_ioctl.c struct qxl_surface surf; surf 406 drivers/gpu/drm/qxl/qxl_ioctl.c surf.format = param->format; surf 407 drivers/gpu/drm/qxl/qxl_ioctl.c surf.width = param->width; surf 408 drivers/gpu/drm/qxl/qxl_ioctl.c surf.height = param->height; surf 409 drivers/gpu/drm/qxl/qxl_ioctl.c surf.stride = param->stride; surf 410 drivers/gpu/drm/qxl/qxl_ioctl.c surf.data = 0; surf 415 drivers/gpu/drm/qxl/qxl_ioctl.c &surf, surf 82 drivers/gpu/drm/qxl/qxl_object.c struct qxl_surface *surf, surf 108 drivers/gpu/drm/qxl/qxl_object.c if (surf) surf 109 drivers/gpu/drm/qxl/qxl_object.c bo->surf = *surf; surf 92 drivers/gpu/drm/qxl/qxl_object.h struct qxl_surface *surf, surf 191 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface *surf, surf 194 drivers/gpu/drm/radeon/evergreen_cs.c surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; surf 195 drivers/gpu/drm/radeon/evergreen_cs.c surf->base_align = surf->bpe; surf 196 drivers/gpu/drm/radeon/evergreen_cs.c surf->palign = 1; surf 197 drivers/gpu/drm/radeon/evergreen_cs.c surf->halign = 1; surf 202 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface *surf, surf 208 drivers/gpu/drm/radeon/evergreen_cs.c palign = MAX(64, track->group_size / surf->bpe); surf 209 drivers/gpu/drm/radeon/evergreen_cs.c surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; surf 210 drivers/gpu/drm/radeon/evergreen_cs.c surf->base_align = track->group_size; surf 211 drivers/gpu/drm/radeon/evergreen_cs.c surf->palign = palign; surf 212 drivers/gpu/drm/radeon/evergreen_cs.c surf->halign = 1; surf 213 drivers/gpu/drm/radeon/evergreen_cs.c if (surf->nbx & (palign - 1)) { surf 216 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->nbx, palign); surf 224 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface *surf, surf 230 drivers/gpu/drm/radeon/evergreen_cs.c palign = track->group_size / (8 * surf->bpe * surf->nsamples); surf 232 drivers/gpu/drm/radeon/evergreen_cs.c surf->layer_size = surf->nbx * surf->nby * surf->bpe; surf 233 drivers/gpu/drm/radeon/evergreen_cs.c surf->base_align = track->group_size; surf 234 drivers/gpu/drm/radeon/evergreen_cs.c surf->palign = palign; surf 235 drivers/gpu/drm/radeon/evergreen_cs.c surf->halign = 8; surf 236 drivers/gpu/drm/radeon/evergreen_cs.c if ((surf->nbx & (palign - 1))) { surf 239 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->nbx, palign, surf 240 drivers/gpu/drm/radeon/evergreen_cs.c track->group_size, surf->bpe, surf->nsamples); surf 244 drivers/gpu/drm/radeon/evergreen_cs.c if ((surf->nby & (8 - 1))) { surf 247 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->nby); surf 255 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface *surf, surf 262 drivers/gpu/drm/radeon/evergreen_cs.c tileb = 64 * surf->bpe * surf->nsamples; surf 264 drivers/gpu/drm/radeon/evergreen_cs.c if (tileb > surf->tsplit) { surf 265 drivers/gpu/drm/radeon/evergreen_cs.c slice_pt = tileb / surf->tsplit; surf 269 drivers/gpu/drm/radeon/evergreen_cs.c palign = (8 * surf->bankw * track->npipes) * surf->mtilea; surf 270 drivers/gpu/drm/radeon/evergreen_cs.c halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; surf 272 drivers/gpu/drm/radeon/evergreen_cs.c mtile_pr = surf->nbx / palign; surf 273 drivers/gpu/drm/radeon/evergreen_cs.c mtile_ps = (mtile_pr * surf->nby) / halign; surf 274 drivers/gpu/drm/radeon/evergreen_cs.c surf->layer_size = mtile_ps * mtileb * slice_pt; surf 275 drivers/gpu/drm/radeon/evergreen_cs.c surf->base_align = (palign / 8) * (halign / 8) * tileb; surf 276 drivers/gpu/drm/radeon/evergreen_cs.c surf->palign = palign; surf 277 drivers/gpu/drm/radeon/evergreen_cs.c surf->halign = halign; surf 279 drivers/gpu/drm/radeon/evergreen_cs.c if ((surf->nbx & (palign - 1))) { surf 282 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->nbx, palign); surf 286 drivers/gpu/drm/radeon/evergreen_cs.c if ((surf->nby & (halign - 1))) { surf 289 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->nby, halign); surf 298 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface *surf, surf 302 drivers/gpu/drm/radeon/evergreen_cs.c surf->bpe = r600_fmt_get_blocksize(surf->format); surf 304 drivers/gpu/drm/radeon/evergreen_cs.c switch (surf->mode) { surf 306 drivers/gpu/drm/radeon/evergreen_cs.c return evergreen_surface_check_linear(p, surf, prefix); surf 308 drivers/gpu/drm/radeon/evergreen_cs.c return evergreen_surface_check_linear_aligned(p, surf, prefix); surf 310 drivers/gpu/drm/radeon/evergreen_cs.c return evergreen_surface_check_1d(p, surf, prefix); surf 312 drivers/gpu/drm/radeon/evergreen_cs.c return evergreen_surface_check_2d(p, surf, prefix); surf 315 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->mode); surf 322 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface *surf, surf 325 drivers/gpu/drm/radeon/evergreen_cs.c switch (surf->mode) { surf 334 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->mode); surf 338 drivers/gpu/drm/radeon/evergreen_cs.c switch (surf->nbanks) { surf 339 drivers/gpu/drm/radeon/evergreen_cs.c case 0: surf->nbanks = 2; break; surf 340 drivers/gpu/drm/radeon/evergreen_cs.c case 1: surf->nbanks = 4; break; surf 341 drivers/gpu/drm/radeon/evergreen_cs.c case 2: surf->nbanks = 8; break; surf 342 drivers/gpu/drm/radeon/evergreen_cs.c case 3: surf->nbanks = 16; break; surf 345 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->nbanks); surf 348 drivers/gpu/drm/radeon/evergreen_cs.c switch (surf->bankw) { surf 349 drivers/gpu/drm/radeon/evergreen_cs.c case 0: surf->bankw = 1; break; surf 350 drivers/gpu/drm/radeon/evergreen_cs.c case 1: surf->bankw = 2; break; surf 351 drivers/gpu/drm/radeon/evergreen_cs.c case 2: surf->bankw = 4; break; surf 352 drivers/gpu/drm/radeon/evergreen_cs.c case 3: surf->bankw = 8; break; surf 355 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->bankw); surf 358 drivers/gpu/drm/radeon/evergreen_cs.c switch (surf->bankh) { surf 359 drivers/gpu/drm/radeon/evergreen_cs.c case 0: surf->bankh = 1; break; surf 360 drivers/gpu/drm/radeon/evergreen_cs.c case 1: surf->bankh = 2; break; surf 361 drivers/gpu/drm/radeon/evergreen_cs.c case 2: surf->bankh = 4; break; surf 362 drivers/gpu/drm/radeon/evergreen_cs.c case 3: surf->bankh = 8; break; surf 365 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->bankh); surf 368 drivers/gpu/drm/radeon/evergreen_cs.c switch (surf->mtilea) { surf 369 drivers/gpu/drm/radeon/evergreen_cs.c case 0: surf->mtilea = 1; break; surf 370 drivers/gpu/drm/radeon/evergreen_cs.c case 1: surf->mtilea = 2; break; surf 371 drivers/gpu/drm/radeon/evergreen_cs.c case 2: surf->mtilea = 4; break; surf 372 drivers/gpu/drm/radeon/evergreen_cs.c case 3: surf->mtilea = 8; break; surf 375 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->mtilea); surf 378 drivers/gpu/drm/radeon/evergreen_cs.c switch (surf->tsplit) { surf 379 drivers/gpu/drm/radeon/evergreen_cs.c case 0: surf->tsplit = 64; break; surf 380 drivers/gpu/drm/radeon/evergreen_cs.c case 1: surf->tsplit = 128; break; surf 381 drivers/gpu/drm/radeon/evergreen_cs.c case 2: surf->tsplit = 256; break; surf 382 drivers/gpu/drm/radeon/evergreen_cs.c case 3: surf->tsplit = 512; break; surf 383 drivers/gpu/drm/radeon/evergreen_cs.c case 4: surf->tsplit = 1024; break; surf 384 drivers/gpu/drm/radeon/evergreen_cs.c case 5: surf->tsplit = 2048; break; surf 385 drivers/gpu/drm/radeon/evergreen_cs.c case 6: surf->tsplit = 4096; break; surf 388 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, prefix, surf->tsplit); surf 397 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface surf; surf 405 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbx = (pitch + 1) * 8; surf 406 drivers/gpu/drm/radeon/evergreen_cs.c surf.nby = ((slice + 1) * 64) / surf.nbx; surf 407 drivers/gpu/drm/radeon/evergreen_cs.c surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]); surf 408 drivers/gpu/drm/radeon/evergreen_cs.c surf.format = G_028C70_FORMAT(track->cb_color_info[id]); surf 409 drivers/gpu/drm/radeon/evergreen_cs.c surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]); surf 410 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]); surf 411 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); surf 412 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); surf 413 drivers/gpu/drm/radeon/evergreen_cs.c surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]); surf 414 drivers/gpu/drm/radeon/evergreen_cs.c surf.nsamples = 1; surf 416 drivers/gpu/drm/radeon/evergreen_cs.c if (!r600_fmt_is_valid_color(surf.format)) { surf 418 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.format, surf 423 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_value_conv_check(p, &surf, "cb"); surf 428 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_check(p, &surf, "cb"); surf 438 drivers/gpu/drm/radeon/evergreen_cs.c if (offset & (surf.base_align - 1)) { surf 440 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, id, offset, surf.base_align); surf 444 drivers/gpu/drm/radeon/evergreen_cs.c offset += surf.layer_size * mslice; surf 450 drivers/gpu/drm/radeon/evergreen_cs.c if (!surf.mode) { surf 455 drivers/gpu/drm/radeon/evergreen_cs.c if (surf.nby > 8) { surf 456 drivers/gpu/drm/radeon/evergreen_cs.c min = surf.nby - 8; surf 460 drivers/gpu/drm/radeon/evergreen_cs.c for (nby = surf.nby; nby > min; nby--) { surf 461 drivers/gpu/drm/radeon/evergreen_cs.c size = nby * surf.nbx * surf.bpe * surf.nsamples; surf 467 drivers/gpu/drm/radeon/evergreen_cs.c surf.nby = nby; surf 468 drivers/gpu/drm/radeon/evergreen_cs.c slice = ((nby * surf.nbx) / 64) - 1; surf 469 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_surface_check(p, &surf, "cb")) { surf 471 drivers/gpu/drm/radeon/evergreen_cs.c tmp += surf.layer_size * mslice; surf 481 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, id, surf.layer_size, surf 485 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.nbx, surf.nby, surf 486 drivers/gpu/drm/radeon/evergreen_cs.c surf.mode, surf.bpe, surf.nsamples, surf 487 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankw, surf.bankh, surf 488 drivers/gpu/drm/radeon/evergreen_cs.c surf.tsplit, surf.mtilea); surf 564 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface surf; surf 572 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbx = (pitch + 1) * 8; surf 573 drivers/gpu/drm/radeon/evergreen_cs.c surf.nby = ((slice + 1) * 64) / surf.nbx; surf 574 drivers/gpu/drm/radeon/evergreen_cs.c surf.mode = G_028040_ARRAY_MODE(track->db_z_info); surf 575 drivers/gpu/drm/radeon/evergreen_cs.c surf.format = G_028044_FORMAT(track->db_s_info); surf 576 drivers/gpu/drm/radeon/evergreen_cs.c surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info); surf 577 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); surf 578 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); surf 579 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); surf 580 drivers/gpu/drm/radeon/evergreen_cs.c surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); surf 581 drivers/gpu/drm/radeon/evergreen_cs.c surf.nsamples = 1; surf 583 drivers/gpu/drm/radeon/evergreen_cs.c if (surf.format != 1) { surf 585 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.format); surf 589 drivers/gpu/drm/radeon/evergreen_cs.c surf.format = V_028C70_COLOR_8; surf 591 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_value_conv_check(p, &surf, "stencil"); surf 596 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_check(p, &surf, NULL); surf 602 drivers/gpu/drm/radeon/evergreen_cs.c surf.format = V_028C70_COLOR_8_8_8_8; surf 603 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_check(p, &surf, "stencil"); surf 613 drivers/gpu/drm/radeon/evergreen_cs.c if (offset & (surf.base_align - 1)) { surf 615 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, offset, surf.base_align); surf 618 drivers/gpu/drm/radeon/evergreen_cs.c offset += surf.layer_size * mslice; surf 622 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.layer_size, surf 632 drivers/gpu/drm/radeon/evergreen_cs.c if (offset & (surf.base_align - 1)) { surf 634 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, offset, surf.base_align); surf 637 drivers/gpu/drm/radeon/evergreen_cs.c offset += surf.layer_size * mslice; surf 641 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.layer_size, surf 649 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); surf 661 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface surf; surf 669 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbx = (pitch + 1) * 8; surf 670 drivers/gpu/drm/radeon/evergreen_cs.c surf.nby = ((slice + 1) * 64) / surf.nbx; surf 671 drivers/gpu/drm/radeon/evergreen_cs.c surf.mode = G_028040_ARRAY_MODE(track->db_z_info); surf 672 drivers/gpu/drm/radeon/evergreen_cs.c surf.format = G_028040_FORMAT(track->db_z_info); surf 673 drivers/gpu/drm/radeon/evergreen_cs.c surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info); surf 674 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); surf 675 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); surf 676 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); surf 677 drivers/gpu/drm/radeon/evergreen_cs.c surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); surf 678 drivers/gpu/drm/radeon/evergreen_cs.c surf.nsamples = 1; surf 680 drivers/gpu/drm/radeon/evergreen_cs.c switch (surf.format) { surf 682 drivers/gpu/drm/radeon/evergreen_cs.c surf.format = V_028C70_COLOR_16; surf 686 drivers/gpu/drm/radeon/evergreen_cs.c surf.format = V_028C70_COLOR_8_8_8_8; surf 690 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.format); surf 694 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_value_conv_check(p, &surf, "depth"); surf 702 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_check(p, &surf, "depth"); surf 711 drivers/gpu/drm/radeon/evergreen_cs.c if (offset & (surf.base_align - 1)) { surf 713 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, offset, surf.base_align); surf 716 drivers/gpu/drm/radeon/evergreen_cs.c offset += surf.layer_size * mslice; surf 720 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.layer_size, surf 727 drivers/gpu/drm/radeon/evergreen_cs.c if (offset & (surf.base_align - 1)) { surf 729 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, offset, surf.base_align); surf 732 drivers/gpu/drm/radeon/evergreen_cs.c offset += surf.layer_size * mslice; surf 736 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.layer_size, surf 744 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); surf 758 drivers/gpu/drm/radeon/evergreen_cs.c struct eg_surface surf; surf 778 drivers/gpu/drm/radeon/evergreen_cs.c surf.format = G_03001C_DATA_FORMAT(texdw[7]); surf 779 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8; surf 780 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx); surf 781 drivers/gpu/drm/radeon/evergreen_cs.c surf.nby = r600_fmt_get_nblocksy(surf.format, height); surf 782 drivers/gpu/drm/radeon/evergreen_cs.c surf.mode = G_030004_ARRAY_MODE(texdw[1]); surf 783 drivers/gpu/drm/radeon/evergreen_cs.c surf.tsplit = G_030018_TILE_SPLIT(texdw[6]); surf 784 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbanks = G_03001C_NUM_BANKS(texdw[7]); surf 785 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankw = G_03001C_BANK_WIDTH(texdw[7]); surf 786 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]); surf 787 drivers/gpu/drm/radeon/evergreen_cs.c surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]); surf 788 drivers/gpu/drm/radeon/evergreen_cs.c surf.nsamples = 1; surf 792 drivers/gpu/drm/radeon/evergreen_cs.c if (!r600_fmt_is_valid_texture(surf.format, p->family)) { surf 794 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.format); surf 807 drivers/gpu/drm/radeon/evergreen_cs.c surf.nsamples = 1 << llevel; surf 819 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_value_conv_check(p, &surf, "texture"); surf 825 drivers/gpu/drm/radeon/evergreen_cs.c evergreen_surface_check(p, &surf, NULL); surf 826 drivers/gpu/drm/radeon/evergreen_cs.c surf.nby = ALIGN(surf.nby, surf.halign); surf 828 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_check(p, &surf, "texture"); surf 837 drivers/gpu/drm/radeon/evergreen_cs.c if (toffset & (surf.base_align - 1)) { surf 839 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, toffset, surf.base_align); surf 842 drivers/gpu/drm/radeon/evergreen_cs.c if (surf.nsamples <= 1 && moffset & (surf.base_align - 1)) { surf 844 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, moffset, surf.base_align); surf 848 drivers/gpu/drm/radeon/evergreen_cs.c toffset += surf.layer_size * depth; surf 850 drivers/gpu/drm/radeon/evergreen_cs.c toffset += surf.layer_size * mslice; surf 855 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.layer_size, surf 858 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbx, surf.nby); surf 879 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbx = r600_fmt_get_nblocksx(surf.format, w); surf 880 drivers/gpu/drm/radeon/evergreen_cs.c surf.nby = r600_fmt_get_nblocksy(surf.format, h); surf 882 drivers/gpu/drm/radeon/evergreen_cs.c switch (surf.mode) { surf 884 drivers/gpu/drm/radeon/evergreen_cs.c if (surf.nbx < surf.palign || surf.nby < surf.halign) { surf 885 drivers/gpu/drm/radeon/evergreen_cs.c surf.mode = ARRAY_1D_TILED_THIN1; surf 888 drivers/gpu/drm/radeon/evergreen_cs.c evergreen_surface_check(p, &surf, NULL); surf 896 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.mode); surf 899 drivers/gpu/drm/radeon/evergreen_cs.c surf.nbx = ALIGN(surf.nbx, surf.palign); surf 900 drivers/gpu/drm/radeon/evergreen_cs.c surf.nby = ALIGN(surf.nby, surf.halign); surf 902 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_surface_check(p, &surf, "mipmap"); surf 908 drivers/gpu/drm/radeon/evergreen_cs.c moffset += surf.layer_size * d; surf 910 drivers/gpu/drm/radeon/evergreen_cs.c moffset += surf.layer_size * mslice; surf 916 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, i, surf.layer_size, surf 921 drivers/gpu/drm/radeon/evergreen_cs.c __func__, __LINE__, surf.nbx, surf.nby, surf 922 drivers/gpu/drm/radeon/evergreen_cs.c surf.mode, surf.bpe, surf.nsamples, surf 923 drivers/gpu/drm/radeon/evergreen_cs.c surf.bankw, surf.bankh, surf 924 drivers/gpu/drm/radeon/evergreen_cs.c surf.tsplit, surf.mtilea); surf 101 drivers/gpu/drm/vc4/vc4_render_cl.c struct drm_vc4_submit_rcl_surface *surf, surf 104 drivers/gpu/drm/vc4/vc4_render_cl.c return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE * surf 385 drivers/gpu/drm/vc4/vc4_render_cl.c struct drm_vc4_submit_rcl_surface *surf) surf 390 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->offset > obj->base.size) { surf 392 drivers/gpu/drm/vc4/vc4_render_cl.c surf->offset, obj->base.size); surf 396 drivers/gpu/drm/vc4/vc4_render_cl.c if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < surf 402 drivers/gpu/drm/vc4/vc4_render_cl.c surf->offset); surf 411 drivers/gpu/drm/vc4/vc4_render_cl.c struct drm_vc4_submit_rcl_surface *surf) surf 413 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->flags != 0 || surf->bits != 0) { surf 418 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->hindex == ~0) surf 421 drivers/gpu/drm/vc4/vc4_render_cl.c *obj = vc4_use_bo(exec, surf->hindex); surf 427 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->offset & 0xf) { surf 432 drivers/gpu/drm/vc4/vc4_render_cl.c return vc4_full_res_bounds_check(exec, *obj, surf); surf 437 drivers/gpu/drm/vc4/vc4_render_cl.c struct drm_vc4_submit_rcl_surface *surf, surf 440 drivers/gpu/drm/vc4/vc4_render_cl.c uint8_t tiling = VC4_GET_FIELD(surf->bits, surf 442 drivers/gpu/drm/vc4/vc4_render_cl.c uint8_t buffer = VC4_GET_FIELD(surf->bits, surf 444 drivers/gpu/drm/vc4/vc4_render_cl.c uint8_t format = VC4_GET_FIELD(surf->bits, surf 449 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { surf 454 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->hindex == ~0) surf 457 drivers/gpu/drm/vc4/vc4_render_cl.c *obj = vc4_use_bo(exec, surf->hindex); surf 464 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { surf 465 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf == &exec->args->zs_write) { surf 470 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->bits != 0) { surf 476 drivers/gpu/drm/vc4/vc4_render_cl.c ret = vc4_full_res_bounds_check(exec, *obj, surf); surf 483 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK | surf 487 drivers/gpu/drm/vc4/vc4_render_cl.c surf->bits); surf 520 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->offset & 0xf) { surf 525 drivers/gpu/drm/vc4/vc4_render_cl.c if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, surf 537 drivers/gpu/drm/vc4/vc4_render_cl.c struct drm_vc4_submit_rcl_surface *surf) surf 539 drivers/gpu/drm/vc4/vc4_render_cl.c uint8_t tiling = VC4_GET_FIELD(surf->bits, surf 541 drivers/gpu/drm/vc4/vc4_render_cl.c uint8_t format = VC4_GET_FIELD(surf->bits, surf 545 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->flags != 0) { surf 550 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK | surf 555 drivers/gpu/drm/vc4/vc4_render_cl.c surf->bits); surf 559 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->hindex == ~0) surf 562 drivers/gpu/drm/vc4/vc4_render_cl.c *obj = vc4_use_bo(exec, surf->hindex); surf 586 drivers/gpu/drm/vc4/vc4_render_cl.c if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, surf 304 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vps->surf) { surf 306 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_resource_unpin(&vps->surf->res); surf 313 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_surface_unreference(&vps->surf); surf 355 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vps->surf) surf 356 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_surface_unreference(&vps->surf); surf 366 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vps->surf = vmw_framebuffer_to_vfbs(fb)->surface; surf 367 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_surface_reference(vps->surf); surf 395 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c du->cursor_surface = vps->surf; surf 398 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vps->surf) { surf 402 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vps->surf->snooper.image, surf 677 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vps->surf) surf 678 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c (void) vmw_surface_reference(vps->surf); surf 733 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vps->surf) surf 734 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_surface_unreference(&vps->surf); surf 287 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct vmw_surface *surf; surf 1008 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c if (vps->surf) surf 1047 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c if (vps->surf) { surf 1049 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_surface_unreference(&vps->surf); surf 1108 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c if (vps->surf) { surf 1109 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct drm_vmw_size cur_base_size = vps->surf->base_size; surf 1113 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vps->surf->format != content_srf.format) { surf 1115 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_surface_unreference(&vps->surf); surf 1120 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c if (!vps->surf) { surf 1134 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c &vps->surf); surf 1147 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c if (vps->surf) { surf 1149 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_surface_unreference(&vps->surf); surf 1152 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vps->surf = vmw_surface_reference(new_vfbs->surface); surf 1155 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c if (vps->surf) { surf 1158 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_resource_pin(&vps->surf->res, false); surf 1180 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_surface_unreference(&vps->surf); surf 1607 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->display_srf = vps->surf;