subslice_mask 1212 drivers/gpu/drm/i915/gem/i915_gem_context.c if (!user->slice_mask || !user->subslice_mask || subslice_mask 1225 drivers/gpu/drm/i915/gem/i915_gem_context.c overflows_type(user->subslice_mask, context->subslice_mask) || subslice_mask 1236 drivers/gpu/drm/i915/gem/i915_gem_context.c if (user->subslice_mask & ~device->subslice_mask[0]) subslice_mask 1243 drivers/gpu/drm/i915/gem/i915_gem_context.c context->subslice_mask = user->subslice_mask; subslice_mask 1250 drivers/gpu/drm/i915/gem/i915_gem_context.c unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]); subslice_mask 1252 drivers/gpu/drm/i915/gem/i915_gem_context.c unsigned int req_ss = hweight8(context->subslice_mask); subslice_mask 2196 drivers/gpu/drm/i915/gem/i915_gem_context.c user_sseu.subslice_mask = ce->sseu.subslice_mask; subslice_mask 934 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c pg_sseu.subslice_mask = subslice_mask 935 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); subslice_mask 593 drivers/gpu/drm/i915/gt/intel_engine_types.h 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0]) subslice_mask 16 drivers/gpu/drm/i915/gt/intel_sseu.c for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) subslice_mask 17 drivers/gpu/drm/i915/gt/intel_sseu.c total += hweight8(sseu->subslice_mask[i]); subslice_mask 25 drivers/gpu/drm/i915/gt/intel_sseu.c return hweight8(sseu->subslice_mask[slice]); subslice_mask 63 drivers/gpu/drm/i915/gt/intel_sseu.c ctx_sseu.subslice_mask = subslice_mask 64 drivers/gpu/drm/i915/gt/intel_sseu.c ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2)); subslice_mask 70 drivers/gpu/drm/i915/gt/intel_sseu.c subslices = hweight8(ctx_sseu.subslice_mask); subslice_mask 99 drivers/gpu/drm/i915/gt/intel_sseu.c subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) { subslice_mask 21 drivers/gpu/drm/i915/gt/intel_sseu.h u8 subslice_mask[GEN_MAX_SLICES]; subslice_mask 48 drivers/gpu/drm/i915/gt/intel_sseu.h u8 subslice_mask; subslice_mask 58 drivers/gpu/drm/i915/gt/intel_sseu.h .subslice_mask = sseu->subslice_mask[0], subslice_mask 799 drivers/gpu/drm/i915/gt/intel_workarounds.c GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask)); subslice_mask 800 drivers/gpu/drm/i915/gt/intel_workarounds.c subslice = fls(l3_en & sseu->subslice_mask[slice]); subslice_mask 803 drivers/gpu/drm/i915/gt/intel_workarounds.c sseu->subslice_mask[slice], l3_en); subslice_mask 3749 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[0] |= BIT(ss); subslice_mask 3797 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[s] = info->sseu.subslice_mask[s]; subslice_mask 3848 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[s] = subslice_mask 3849 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; subslice_mask 3859 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[s] |= BIT(ss); subslice_mask 3885 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[s] = subslice_mask 3886 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; subslice_mask 149 drivers/gpu/drm/i915/i915_getparam.c value = sseu->subslice_mask[0]; subslice_mask 86 drivers/gpu/drm/i915/i915_query.c sseu->subslice_mask, subslice_length)) subslice_mask 98 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s]); subslice_mask 165 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s]); subslice_mask 215 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask; subslice_mask 217 drivers/gpu/drm/i915/intel_device_info.c if (sseu->subslice_mask[s] & BIT(ss)) subslice_mask 237 drivers/gpu/drm/i915/intel_device_info.c u32 subslice_mask, eu_en; subslice_mask 245 drivers/gpu/drm/i915/intel_device_info.c subslice_mask = (1 << 4) - 1; subslice_mask 246 drivers/gpu/drm/i915/intel_device_info.c subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> subslice_mask 253 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = subslice_mask; subslice_mask 255 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] = subslice_mask & 0x3; subslice_mask 286 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] &= ~BIT(ss); subslice_mask 328 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] |= BIT(0); subslice_mask 339 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] |= BIT(1); subslice_mask 368 drivers/gpu/drm/i915/intel_device_info.c u32 fuse2, eu_disable, subslice_mask; subslice_mask 383 drivers/gpu/drm/i915/intel_device_info.c subslice_mask = (1 << sseu->max_subslices) - 1; subslice_mask 384 drivers/gpu/drm/i915/intel_device_info.c subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> subslice_mask 396 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] = subslice_mask; subslice_mask 403 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->subslice_mask[s] & BIT(ss))) subslice_mask 452 drivers/gpu/drm/i915/intel_device_info.c #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) subslice_mask 453 drivers/gpu/drm/i915/intel_device_info.c info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; subslice_mask 472 drivers/gpu/drm/i915/intel_device_info.c u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ subslice_mask 484 drivers/gpu/drm/i915/intel_device_info.c subslice_mask = GENMASK(sseu->max_subslices - 1, 0); subslice_mask 485 drivers/gpu/drm/i915/intel_device_info.c subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> subslice_mask 505 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] = subslice_mask; subslice_mask 511 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->subslice_mask[s] & BIT(ss))) subslice_mask 567 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = BIT(0); subslice_mask 571 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = BIT(0) | BIT(1); subslice_mask 575 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = BIT(0) | BIT(1); subslice_mask 576 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[1] = BIT(0) | BIT(1); subslice_mask 581 drivers/gpu/drm/i915/intel_device_info.c sseu->max_subslices = hweight8(sseu->subslice_mask[0]); subslice_mask 1616 include/uapi/drm/i915_drm.h __u64 subslice_mask; subslice_mask 1616 tools/include/uapi/drm/i915_drm.h __u64 subslice_mask;