subc 106 drivers/gpu/drm/i2c/ch7006_mode.c subc, scale, scale_mask, norm_mask, e_hd, e_vd) { \ subc 128 drivers/gpu/drm/i2c/ch7006_mode.c .subc_coeff = subc * fixed1, \ subc 136 drivers/gpu/drm/i2c/ch7006_mode.c subc, scale, scale_mask, norm_mask) \ subc 137 drivers/gpu/drm/i2c/ch7006_mode.c __MODE(f, hd, vd, ht, vt, hsynp, vsynp, subc, scale, \ subc 13 drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h bool nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data); subc 109 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) subc 111 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); subc 115 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) subc 117 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); subc 121 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) subc 123 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); subc 127 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) subc 129 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); subc 133 drivers/gpu/drm/nouveau/nouveau_dma.h BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) subc 135 drivers/gpu/drm/nouveau/nouveau_dma.h OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); subc 51 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c u32 subc = (addr & 0x3800) >> 11; subc 61 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c subc, mthd, data); subc 413 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 subc = (addr & 0x00070000) >> 16; subc 422 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) subc 434 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c subc, mthd, data); subc 693 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 subc = (addr & 0x00070000) >> 16; subc 702 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) subc 716 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c subc, mthd, data); subc 111 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c const int subc = (addr & 0x0000e000) >> 13; subc 113 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c const u32 mask = 0x0000000f << (subc * 4); subc 127 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c handled = nvkm_sw_mthd(sw, chid, subc, mthd, data); subc 1517 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 subc = (addr & 0x00070000) >> 16; subc 1523 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c subc, class, mthd, data); subc 1557 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 subc = (addr & 0x00070000) >> 16; subc 1570 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (device->card_type < NV_E0 || subc < 4) subc 1571 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c class = nvkm_rd32(device, 0x404200 + (subc * 4)); subc 1588 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c chid, inst << 12, name, subc, subc 1598 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c chid, inst << 12, name, subc, class, mthd, data); subc 1609 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c name, subc, class, mthd, data); subc 447 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c int subc = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; subc 456 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nvkm_wr32(device, NV04_PGRAPH_CTX_CACHE1 + (subc << 2), tmp); subc 1282 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 subc = (addr & 0x0000e000) >> 13; subc 1285 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff; subc 1321 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c subc, class, mthd, data); subc 1091 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c u32 subc = (addr & 0x00070000) >> 16; subc 1094 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; subc 1129 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c subc, class, mthd, data); subc 191 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c u32 subc = (addr & 0x00070000) >> 16; subc 194 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; subc 213 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c subc, class, mthd, data); subc 243 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 subc = (addr & 0x00070000) >> 16; subc 246 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff; subc 280 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c subc, class, mthd, data); subc 423 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 subc = (addr & 0x00070000) >> 16; subc 436 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c chid, inst, name, subc, class, mthd, subc 451 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 subc = (addr & 0x00070000) >> 16; subc 462 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c subc, class, mthd, data, addr); subc 629 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c u32 subc = (addr & 0x00070000) >> 16; subc 669 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c subc, class, mthd, data); subc 50 drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c u32 subc = (addr & 0x3800) >> 11; subc 60 drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c subc, mthd, data); subc 30 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data) subc 39 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c handled = nvkm_sw_chan_mthd(chan, subc, mthd, data); subc 33 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c nvkm_sw_chan_mthd(struct nvkm_sw_chan *chan, int subc, u32 mthd, u32 data) subc 43 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c return chan->func->mthd(chan, subc, mthd, data); subc 22 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h bool (*mthd)(struct nvkm_sw_chan *, int subc, u32 mthd, u32 data); subc 28 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h bool nvkm_sw_chan_mthd(struct nvkm_sw_chan *, int subc, u32 mthd, u32 data); subc 57 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c gf100_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) subc 88 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c nv04_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) subc 62 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c nv50_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data)