subblock          343 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h)                             \
subblock          344 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	[AMDGPU_RAS_BLOCK__##subblock] = {                                     \
subblock          345 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		#subblock,                                                     \
subblock          346 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		TA_RAS_BLOCK__##subblock,                                      \
subblock          343 drivers/net/dsa/vitesse-vsc73xx-core.c int vsc73xx_is_addr_valid(u8 block, u8 subblock)
subblock          347 drivers/net/dsa/vitesse-vsc73xx-core.c 		switch (subblock) {
subblock          356 drivers/net/dsa/vitesse-vsc73xx-core.c 		switch (subblock) {
subblock          365 drivers/net/dsa/vitesse-vsc73xx-core.c 		switch (subblock) {
subblock          376 drivers/net/dsa/vitesse-vsc73xx-core.c static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
subblock          379 drivers/net/dsa/vitesse-vsc73xx-core.c 	return vsc->ops->read(vsc, block, subblock, reg, val);
subblock          382 drivers/net/dsa/vitesse-vsc73xx-core.c static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
subblock          385 drivers/net/dsa/vitesse-vsc73xx-core.c 	return vsc->ops->write(vsc, block, subblock, reg, val);
subblock          388 drivers/net/dsa/vitesse-vsc73xx-core.c static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock,
subblock          395 drivers/net/dsa/vitesse-vsc73xx-core.c 	ret = vsc73xx_read(vsc, block, subblock, reg, &orig);
subblock          400 drivers/net/dsa/vitesse-vsc73xx-core.c 	return vsc73xx_write(vsc, block, subblock, reg, tmp);
subblock           42 drivers/net/dsa/vitesse-vsc73xx-platform.c static u32 vsc73xx_make_addr(u8 block, u8 subblock, u8 reg)
subblock           48 drivers/net/dsa/vitesse-vsc73xx-platform.c 	ret |= (subblock & VSC73XX_CMD_PLATFORM_SUBBLOCK_MASK)
subblock           55 drivers/net/dsa/vitesse-vsc73xx-platform.c static int vsc73xx_platform_read(struct vsc73xx *vsc, u8 block, u8 subblock,
subblock           61 drivers/net/dsa/vitesse-vsc73xx-platform.c 	if (!vsc73xx_is_addr_valid(block, subblock))
subblock           64 drivers/net/dsa/vitesse-vsc73xx-platform.c 	offset = vsc73xx_make_addr(block, subblock, reg);
subblock           73 drivers/net/dsa/vitesse-vsc73xx-platform.c static int vsc73xx_platform_write(struct vsc73xx *vsc, u8 block, u8 subblock,
subblock           79 drivers/net/dsa/vitesse-vsc73xx-platform.c 	if (!vsc73xx_is_addr_valid(block, subblock))
subblock           82 drivers/net/dsa/vitesse-vsc73xx-platform.c 	offset = vsc73xx_make_addr(block, subblock, reg);
subblock           40 drivers/net/dsa/vitesse-vsc73xx-spi.c static u8 vsc73xx_make_addr(u8 mode, u8 block, u8 subblock)
subblock           47 drivers/net/dsa/vitesse-vsc73xx-spi.c 	ret |= subblock & VSC73XX_CMD_SPI_SUBBLOCK_MASK;
subblock           52 drivers/net/dsa/vitesse-vsc73xx-spi.c static int vsc73xx_spi_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
subblock           62 drivers/net/dsa/vitesse-vsc73xx-spi.c 	if (!vsc73xx_is_addr_valid(block, subblock))
subblock           77 drivers/net/dsa/vitesse-vsc73xx-spi.c 	cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_SPI_MODE_READ, block, subblock);
subblock           94 drivers/net/dsa/vitesse-vsc73xx-spi.c static int vsc73xx_spi_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
subblock          104 drivers/net/dsa/vitesse-vsc73xx-spi.c 	if (!vsc73xx_is_addr_valid(block, subblock))
subblock          119 drivers/net/dsa/vitesse-vsc73xx-spi.c 	cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_SPI_MODE_WRITE, block, subblock);
subblock           21 drivers/net/dsa/vitesse-vsc73xx.h 	int (*read)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
subblock           23 drivers/net/dsa/vitesse-vsc73xx.h 	int (*write)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
subblock           27 drivers/net/dsa/vitesse-vsc73xx.h int vsc73xx_is_addr_valid(u8 block, u8 subblock);
subblock           54 drivers/spi/spi-fsl-cpm.c 		qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
subblock          257 drivers/spi/spi-fsl-cpm.c 		qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
subblock          292 drivers/spi/spi-fsl-cpm.c 			mspi->subblock = *iprop;
subblock          294 drivers/spi/spi-fsl-cpm.c 		switch (mspi->subblock) {
subblock          299 drivers/spi/spi-fsl-cpm.c 			mspi->subblock = QE_CR_SUBBLOCK_SPI1;
subblock          302 drivers/spi/spi-fsl-cpm.c 			mspi->subblock = QE_CR_SUBBLOCK_SPI2;
subblock           28 drivers/spi/spi-fsl-lib.h 	int subblock;