stxx_spi4_dat     356 arch/mips/cavium-octeon/executive/cvmx-spi.c 		union cvmx_stxx_spi4_dat stxx_spi4_dat;
stxx_spi4_dat     383 arch/mips/cavium-octeon/executive/cvmx-spi.c 		stxx_spi4_dat.u64 = 0;
stxx_spi4_dat     385 arch/mips/cavium-octeon/executive/cvmx-spi.c 		stxx_spi4_dat.s.alpha = 32;
stxx_spi4_dat     386 arch/mips/cavium-octeon/executive/cvmx-spi.c 		stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */
stxx_spi4_dat     388 arch/mips/cavium-octeon/executive/cvmx-spi.c 			       stxx_spi4_dat.u64);