stx_int_msk 344 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c union cvmx_stxx_int_msk stx_int_msk; stx_int_msk 347 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.u64 = 0; stx_int_msk 350 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.frmerr = 1; stx_int_msk 351 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.unxfrm = 1; stx_int_msk 352 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.nosync = 1; stx_int_msk 353 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.diperr = 1; stx_int_msk 354 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.datovr = 1; stx_int_msk 355 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.ovrbst = 1; stx_int_msk 356 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.calpar1 = 1; stx_int_msk 357 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.calpar0 = 1; stx_int_msk 361 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.frmerr = 1; stx_int_msk 362 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.unxfrm = 1; stx_int_msk 363 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.nosync = 1; stx_int_msk 364 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.diperr = 1; stx_int_msk 365 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.datovr = 1; stx_int_msk 366 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.ovrbst = 1; stx_int_msk 367 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.calpar1 = 1; stx_int_msk 368 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c stx_int_msk.s.calpar0 = 1; stx_int_msk 370 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);