stream_ctrl      2627 drivers/gpu/drm/radeon/evergreen.c 	unsigned stream_ctrl;
stream_ctrl      2636 drivers/gpu/drm/radeon/evergreen.c 	stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
stream_ctrl      2638 drivers/gpu/drm/radeon/evergreen.c 	if (!(stream_ctrl & EVERGREEN_DP_VID_STREAM_CNTL_ENABLE)) {
stream_ctrl      2643 drivers/gpu/drm/radeon/evergreen.c 	stream_ctrl &=~EVERGREEN_DP_VID_STREAM_CNTL_ENABLE;
stream_ctrl      2645 drivers/gpu/drm/radeon/evergreen.c 	       evergreen_dp_offsets[dig_fe], stream_ctrl);
stream_ctrl      2647 drivers/gpu/drm/radeon/evergreen.c 	stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
stream_ctrl      2649 drivers/gpu/drm/radeon/evergreen.c 	while (counter < 32 && stream_ctrl & EVERGREEN_DP_VID_STREAM_STATUS) {
stream_ctrl      2652 drivers/gpu/drm/radeon/evergreen.c 		stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
stream_ctrl       397 drivers/media/dvb-frontends/as102_fe.c 	return state->ops->stream_ctrl(state->priv, acquire,
stream_ctrl        14 drivers/media/dvb-frontends/as102_fe.h 	int (*stream_ctrl)(void *priv, int acquire, uint32_t elna_cfg);
stream_ctrl       282 drivers/media/usb/as102/as102_drv.c 	.stream_ctrl = as102_stream_ctrl,