SamuLevel 1090 drivers/gpu/drm/amd/amdgpu/kv_dpm.c offsetof(SMU7_Fusion_DpmTable, SamuLevel), SamuLevel 273 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU]; SamuLevel 257 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h SMU73_Discrete_ExtClkLevel SamuLevel [SMU73_MAX_LEVELS_SAMU]; SamuLevel 289 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h SMU74_Discrete_ExtClkLevel SamuLevel[SMU74_MAX_LEVELS_SAMU]; SamuLevel 295 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h SMU75_Discrete_ExtClkLevel SamuLevel [SMU75_MAX_LEVELS_SAMU]; SamuLevel 331 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; SamuLevel 238 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h SMU7_Fusion_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; SamuLevel 2767 drivers/gpu/drm/radeon/ci_dpm.c table->SamuLevel[count].Frequency = SamuLevel 2769 drivers/gpu/drm/radeon/ci_dpm.c table->SamuLevel[count].MinVoltage = SamuLevel 2771 drivers/gpu/drm/radeon/ci_dpm.c table->SamuLevel[count].MinPhases = 1; SamuLevel 2775 drivers/gpu/drm/radeon/ci_dpm.c table->SamuLevel[count].Frequency, false, ÷rs); SamuLevel 2779 drivers/gpu/drm/radeon/ci_dpm.c table->SamuLevel[count].Divider = (u8)dividers.post_divider; SamuLevel 2781 drivers/gpu/drm/radeon/ci_dpm.c table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); SamuLevel 2782 drivers/gpu/drm/radeon/ci_dpm.c table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); SamuLevel 1008 drivers/gpu/drm/radeon/kv_dpm.c offsetof(SMU7_Fusion_DpmTable, SamuLevel), SamuLevel 330 drivers/gpu/drm/radeon/smu7_discrete.h SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; SamuLevel 238 drivers/gpu/drm/radeon/smu7_fusion.h SMU7_Fusion_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU];