state_offset      106 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 	u32 *ptr, unsigned int state_offset, unsigned int num)
state_offset      108 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 	unsigned int size = min(ETNAVIV_STATES_SIZE, state_offset + num);
state_offset      109 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 	unsigned int st_offset = state_offset, buf_offset;
state_offset      113 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 			      st_offset - state_offset) * 4;
state_offset      107 drivers/gpu/drm/i915/gvt/scheduler.c 			u32 state_offset = ctx_flexeu0 + i * 2;
state_offset      109 drivers/gpu/drm/i915/gvt/scheduler.c 			workload->flex_mmio[i] = reg_state[state_offset + 1];
state_offset      117 drivers/gpu/drm/i915/gvt/scheduler.c 			u32 state_offset = ctx_flexeu0 + i * 2;
state_offset      120 drivers/gpu/drm/i915/gvt/scheduler.c 			reg_state[state_offset] = mmio;
state_offset      121 drivers/gpu/drm/i915/gvt/scheduler.c 			reg_state[state_offset + 1] = workload->flex_mmio[i];
state_offset      148 drivers/net/dsa/mv88e6xxx/global1_vtu.c 		unsigned int state_offset = member_offset + 2;
state_offset      151 drivers/net/dsa/mv88e6xxx/global1_vtu.c 		entry->state[i] = (regs[i / 4] >> state_offset) & 0x3;
state_offset      166 drivers/net/dsa/mv88e6xxx/global1_vtu.c 		unsigned int state_offset = member_offset + 2;
state_offset      169 drivers/net/dsa/mv88e6xxx/global1_vtu.c 		regs[i / 4] |= (entry->state[i] & 0x3) << state_offset;
state_offset       24 lib/lzo/lzo1x_compress.c 		    size_t ti, void *wrkmem, signed char *state_offset,
state_offset      120 lib/lzo/lzo1x_compress.c 				op[*state_offset] |= t;
state_offset      160 lib/lzo/lzo1x_compress.c 			*state_offset = -3;
state_offset      295 lib/lzo/lzo1x_compress.c 		*state_offset = -2;
state_offset      313 lib/lzo/lzo1x_compress.c 	signed char state_offset = -2;
state_offset      336 lib/lzo/lzo1x_compress.c 					&state_offset, bitstream_version);
state_offset      349 lib/lzo/lzo1x_compress.c 			op[state_offset] |= t;