start_slope_cntl_r   87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 	REG_SET(reg->start_slope_cntl_r, 0,
start_slope_cntl_r   47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h 	uint32_t start_slope_cntl_r; \
start_slope_cntl_r  396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMA_SLOPE_CNTL_R);
start_slope_cntl_r  425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMB_SLOPE_CNTL_R);
start_slope_cntl_r  549 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMB_SLOPE_CNTL_R);
start_slope_cntl_r  578 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMA_SLOPE_CNTL_R);
start_slope_cntl_r  248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_R);
start_slope_cntl_r  276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_R);
start_slope_cntl_r  299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]);
start_slope_cntl_r  326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]);