start_reg         225 drivers/base/regmap/regmap-debugfs.c 	unsigned int val, start_reg;
start_reg         237 drivers/base/regmap/regmap-debugfs.c 	start_reg = regmap_debugfs_get_dump_start(map, from, *ppos, &p);
start_reg         239 drivers/base/regmap/regmap-debugfs.c 	for (i = start_reg; i >= 0 && i <= to;
start_reg        1780 drivers/gpu/drm/radeon/evergreen_cs.c 	unsigned start_reg, end_reg, reg;
start_reg        2301 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
start_reg        2302 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2303 drivers/gpu/drm/radeon/evergreen_cs.c 		if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
start_reg        2304 drivers/gpu/drm/radeon/evergreen_cs.c 		    (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
start_reg        2309 drivers/gpu/drm/radeon/evergreen_cs.c 		for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
start_reg        2318 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
start_reg        2319 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2320 drivers/gpu/drm/radeon/evergreen_cs.c 		if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
start_reg        2321 drivers/gpu/drm/radeon/evergreen_cs.c 		    (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
start_reg        2326 drivers/gpu/drm/radeon/evergreen_cs.c 		for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
start_reg        2339 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
start_reg        2340 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2341 drivers/gpu/drm/radeon/evergreen_cs.c 		if ((start_reg < PACKET3_SET_RESOURCE_START) ||
start_reg        2342 drivers/gpu/drm/radeon/evergreen_cs.c 		    (start_reg >= PACKET3_SET_RESOURCE_END) ||
start_reg        2442 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
start_reg        2443 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2444 drivers/gpu/drm/radeon/evergreen_cs.c 		if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
start_reg        2445 drivers/gpu/drm/radeon/evergreen_cs.c 		    (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
start_reg        2452 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
start_reg        2453 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2454 drivers/gpu/drm/radeon/evergreen_cs.c 		if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
start_reg        2455 drivers/gpu/drm/radeon/evergreen_cs.c 		    (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
start_reg        2462 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
start_reg        2463 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2464 drivers/gpu/drm/radeon/evergreen_cs.c 		if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
start_reg        2465 drivers/gpu/drm/radeon/evergreen_cs.c 		    (start_reg >= PACKET3_SET_CTL_CONST_END) ||
start_reg        2476 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
start_reg        2477 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2478 drivers/gpu/drm/radeon/evergreen_cs.c 		if ((start_reg < PACKET3_SET_SAMPLER_START) ||
start_reg        2479 drivers/gpu/drm/radeon/evergreen_cs.c 		    (start_reg >= PACKET3_SET_SAMPLER_END) ||
start_reg        3353 drivers/gpu/drm/radeon/evergreen_cs.c 	u32 start_reg, end_reg, reg, i;
start_reg        3422 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
start_reg        3423 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        3424 drivers/gpu/drm/radeon/evergreen_cs.c 		if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
start_reg        3425 drivers/gpu/drm/radeon/evergreen_cs.c 		    (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
start_reg        3431 drivers/gpu/drm/radeon/evergreen_cs.c 			reg = start_reg + (4 * i);
start_reg        3454 drivers/gpu/drm/radeon/evergreen_cs.c 				start_reg = idx_value << 2;
start_reg        3456 drivers/gpu/drm/radeon/evergreen_cs.c 					reg = start_reg;
start_reg        3463 drivers/gpu/drm/radeon/evergreen_cs.c 						reg = start_reg + (4 * i);
start_reg        3475 drivers/gpu/drm/radeon/evergreen_cs.c 				start_reg = ib[idx + 2];
start_reg        3477 drivers/gpu/drm/radeon/evergreen_cs.c 					reg = start_reg;
start_reg        3484 drivers/gpu/drm/radeon/evergreen_cs.c 						reg = start_reg + (4 * i);
start_reg        1634 drivers/gpu/drm/radeon/r600_cs.c 	unsigned start_reg, end_reg, reg;
start_reg        1909 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
start_reg        1910 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        1911 drivers/gpu/drm/radeon/r600_cs.c 		if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
start_reg        1912 drivers/gpu/drm/radeon/r600_cs.c 		    (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
start_reg        1918 drivers/gpu/drm/radeon/r600_cs.c 			reg = start_reg + (4 * i);
start_reg        1925 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
start_reg        1926 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        1927 drivers/gpu/drm/radeon/r600_cs.c 		if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
start_reg        1928 drivers/gpu/drm/radeon/r600_cs.c 		    (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
start_reg        1934 drivers/gpu/drm/radeon/r600_cs.c 			reg = start_reg + (4 * i);
start_reg        1945 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
start_reg        1946 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        1947 drivers/gpu/drm/radeon/r600_cs.c 		if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
start_reg        1948 drivers/gpu/drm/radeon/r600_cs.c 		    (start_reg >= PACKET3_SET_RESOURCE_END) ||
start_reg        2025 drivers/gpu/drm/radeon/r600_cs.c 			start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
start_reg        2026 drivers/gpu/drm/radeon/r600_cs.c 			end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2027 drivers/gpu/drm/radeon/r600_cs.c 			if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
start_reg        2028 drivers/gpu/drm/radeon/r600_cs.c 			    (start_reg >= PACKET3_SET_ALU_CONST_END) ||
start_reg        2036 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
start_reg        2037 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2038 drivers/gpu/drm/radeon/r600_cs.c 		if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
start_reg        2039 drivers/gpu/drm/radeon/r600_cs.c 		    (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
start_reg        2046 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
start_reg        2047 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2048 drivers/gpu/drm/radeon/r600_cs.c 		if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
start_reg        2049 drivers/gpu/drm/radeon/r600_cs.c 		    (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
start_reg        2056 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
start_reg        2057 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2058 drivers/gpu/drm/radeon/r600_cs.c 		if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
start_reg        2059 drivers/gpu/drm/radeon/r600_cs.c 		    (start_reg >= PACKET3_SET_CTL_CONST_END) ||
start_reg        2070 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
start_reg        2071 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        2072 drivers/gpu/drm/radeon/r600_cs.c 		if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
start_reg        2073 drivers/gpu/drm/radeon/r600_cs.c 		    (start_reg >= PACKET3_SET_SAMPLER_END) ||
start_reg        4481 drivers/gpu/drm/radeon/si.c 	u32 start_reg, reg, i;
start_reg        4488 drivers/gpu/drm/radeon/si.c 			start_reg = idx_value << 2;
start_reg        4490 drivers/gpu/drm/radeon/si.c 				reg = start_reg;
start_reg        4497 drivers/gpu/drm/radeon/si.c 					reg = start_reg + (4 * i);
start_reg        4509 drivers/gpu/drm/radeon/si.c 			start_reg = ib[idx + 2];
start_reg        4511 drivers/gpu/drm/radeon/si.c 				reg = start_reg;
start_reg        4518 drivers/gpu/drm/radeon/si.c 					reg = start_reg + (4 * i);
start_reg        4536 drivers/gpu/drm/radeon/si.c 	u32 start_reg, end_reg, reg, i;
start_reg        4594 drivers/gpu/drm/radeon/si.c 			start_reg = ib[idx + 1] * 4;
start_reg        4596 drivers/gpu/drm/radeon/si.c 				if (!si_vm_reg_valid(start_reg))
start_reg        4600 drivers/gpu/drm/radeon/si.c 					reg = start_reg + (4 * i);
start_reg        4622 drivers/gpu/drm/radeon/si.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
start_reg        4623 drivers/gpu/drm/radeon/si.c 		end_reg = 4 * pkt->count + start_reg - 4;
start_reg        4624 drivers/gpu/drm/radeon/si.c 		if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
start_reg        4625 drivers/gpu/drm/radeon/si.c 		    (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
start_reg        4631 drivers/gpu/drm/radeon/si.c 			reg = start_reg + (4 * i);
start_reg        4654 drivers/gpu/drm/radeon/si.c 	u32 start_reg, reg, i;
start_reg        4697 drivers/gpu/drm/radeon/si.c 			start_reg = ib[idx + 1] * 4;
start_reg        4699 drivers/gpu/drm/radeon/si.c 				if (!si_vm_reg_valid(start_reg))
start_reg        4703 drivers/gpu/drm/radeon/si.c 					reg = start_reg + (4 * i);
start_reg        2337 drivers/hwmon/f71882fg.c 	u8 start_reg, reg;
start_reg        2352 drivers/hwmon/f71882fg.c 	start_reg = f71882fg_read8(data, F71882FG_REG_START);
start_reg        2353 drivers/hwmon/f71882fg.c 	if (start_reg & 0x04) {
start_reg        2357 drivers/hwmon/f71882fg.c 	if (!(start_reg & 0x03)) {
start_reg        2367 drivers/hwmon/f71882fg.c 	if (start_reg & 0x01) {
start_reg        2437 drivers/hwmon/f71882fg.c 	if (start_reg & 0x02) {
start_reg        2508 drivers/hwmon/f71882fg.c 	u8 start_reg = f71882fg_read8(data, F71882FG_REG_START);
start_reg        2515 drivers/hwmon/f71882fg.c 	if (start_reg & 0x01) {
start_reg        2568 drivers/hwmon/f71882fg.c 	if (start_reg & 0x02) {
start_reg         565 drivers/i2c/busses/i2c-mt65xx.c 	u16 start_reg;
start_reg         730 drivers/i2c/busses/i2c-mt65xx.c 		start_reg = I2C_TRANSAC_START;
start_reg         732 drivers/i2c/busses/i2c-mt65xx.c 		start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
start_reg         734 drivers/i2c/busses/i2c-mt65xx.c 			start_reg |= I2C_RS_MUL_CNFG;
start_reg         736 drivers/i2c/busses/i2c-mt65xx.c 	mtk_i2c_writew(i2c, start_reg, OFFSET_START);
start_reg         602 drivers/iio/light/si1133.c static int si1133_bulk_read(struct si1133_data *data, u8 start_reg, u8 length,
start_reg         611 drivers/iio/light/si1133.c 	return regmap_bulk_read(data->regmap, start_reg, buffer, length);
start_reg         102 drivers/iio/light/vl6180.c 	u16 start_reg, value_reg;
start_reg         109 drivers/iio/light/vl6180.c 		.start_reg = VL6180_ALS_START,
start_reg         115 drivers/iio/light/vl6180.c 		.start_reg = VL6180_RANGE_START,
start_reg         121 drivers/iio/light/vl6180.c 		.start_reg = VL6180_RANGE_START,
start_reg         216 drivers/iio/light/vl6180.c 		vl6180_chan_regs_table[addr].start_reg, VL6180_STARTSTOP);
start_reg          41 drivers/input/touchscreen/st1232.c 	u8	start_reg;
start_reg          63 drivers/input/touchscreen/st1232.c 	u8 start_reg = ts->chip_info->start_reg;
start_reg          70 drivers/input/touchscreen/st1232.c 	msg[0].buf = &start_reg;
start_reg         163 drivers/input/touchscreen/st1232.c 	.start_reg	= 0x12,
start_reg         172 drivers/input/touchscreen/st1232.c 	.start_reg	= 0x12,
start_reg         100 drivers/mfd/wm8350-core.c int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
start_reg         105 drivers/mfd/wm8350-core.c 	err = regmap_bulk_read(wm8350->regmap, start_reg, dest, regs);
start_reg         108 drivers/mfd/wm8350-core.c 			start_reg);
start_reg         114 drivers/mfd/wm8350-core.c int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
start_reg         119 drivers/mfd/wm8350-core.c 	ret = regmap_bulk_write(wm8350->regmap, start_reg, src, regs);
start_reg         122 drivers/mfd/wm8350-core.c 			start_reg);
start_reg         713 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 	u32 start_reg = 0;
start_reg         723 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
start_reg         726 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			start_reg = PXP2_REG_PSWRQ_QM0_L2P;
start_reg         729 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
start_reg         732 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			start_reg = PXP2_REG_PSWRQ_TM0_L2P;
start_reg         735 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 		REG_WR(bp, start_reg + BP_FUNC(bp)*4,
start_reg         741 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
start_reg         745 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
start_reg         749 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
start_reg         753 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
start_reg         757 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 		REG_WR(bp, start_reg, (ilt_start + ilt_cli->start));