start_end_cntl2_r 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_end_cntl2_r, 0, start_end_cntl2_r 53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_end_cntl2_r; \ start_end_cntl2_r 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMA_END_CNTL2_R); start_end_cntl2_r 431 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMB_END_CNTL2_R); start_end_cntl2_r 555 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMB_END_CNTL2_R); start_end_cntl2_r 584 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMA_END_CNTL2_R); start_end_cntl2_r 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); start_end_cntl2_r 282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); start_end_cntl2_r 305 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]); start_end_cntl2_r 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]);