start_end_cntl2_g   98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 	REG_SET_2(reg->start_end_cntl2_g, 0,
start_end_cntl2_g   51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h 	uint32_t start_end_cntl2_g; \
start_end_cntl2_g  400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMA_END_CNTL2_G);
start_end_cntl2_g  429 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMB_END_CNTL2_G);
start_end_cntl2_g  553 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMB_END_CNTL2_G);
start_end_cntl2_g  582 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMA_END_CNTL2_G);
start_end_cntl2_g  252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
start_end_cntl2_g  280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
start_end_cntl2_g  303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]);
start_end_cntl2_g  330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]);