start_end_cntl2_b 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_end_cntl2_b, 0, start_end_cntl2_b 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_end_cntl2_b; \ start_end_cntl2_b 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMA_END_CNTL2_B); start_end_cntl2_b 427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMB_END_CNTL2_B); start_end_cntl2_b 551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMB_END_CNTL2_B); start_end_cntl2_b 580 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMA_END_CNTL2_B); start_end_cntl2_b 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); start_end_cntl2_b 278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); start_end_cntl2_b 301 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]); start_end_cntl2_b 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]);