start_end_cntl1_r  102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 	REG_SET(reg->start_end_cntl1_r, 0,
start_end_cntl1_r   52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h 	uint32_t start_end_cntl1_r; \
start_end_cntl1_r  401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMA_END_CNTL1_R);
start_end_cntl1_r  430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMB_END_CNTL1_R);
start_end_cntl1_r  554 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMB_END_CNTL1_R);
start_end_cntl1_r  583 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMA_END_CNTL1_R);
start_end_cntl1_r  253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
start_end_cntl1_r  281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
start_end_cntl1_r  304 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]);
start_end_cntl1_r  331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]);