start_end_cntl1_g   96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 	REG_SET(reg->start_end_cntl1_g, 0,
start_end_cntl1_g   50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h 	uint32_t start_end_cntl1_g; \
start_end_cntl1_g  399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMA_END_CNTL1_G);
start_end_cntl1_g  428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMB_END_CNTL1_G);
start_end_cntl1_g  552 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMB_END_CNTL1_G);
start_end_cntl1_g  581 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMA_END_CNTL1_G);
start_end_cntl1_g  251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
start_end_cntl1_g  279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
start_end_cntl1_g  302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]);
start_end_cntl1_g  329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]);