start_end_cntl1_b 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_end_cntl1_b, 0, start_end_cntl1_b 48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_end_cntl1_b; \ start_end_cntl1_b 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMA_END_CNTL1_B); start_end_cntl1_b 426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMB_END_CNTL1_B); start_end_cntl1_b 550 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMB_END_CNTL1_B); start_end_cntl1_b 579 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMA_END_CNTL1_B); start_end_cntl1_b 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); start_end_cntl1_b 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); start_end_cntl1_b 300 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]); start_end_cntl1_b 327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);