start_cntl_r 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_cntl_r, 0, start_cntl_r 44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_cntl_r; \ start_cntl_r 393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_RGAM_RAMA_START_CNTL_R); start_cntl_r 422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_RGAM_RAMB_START_CNTL_R); start_cntl_r 546 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_DGAM_RAMB_START_CNTL_R); start_cntl_r 575 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_DGAM_RAMA_START_CNTL_R); start_cntl_r 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); start_cntl_r 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); start_cntl_r 296 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]); start_cntl_r 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);