start_cntl_g 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_cntl_g, 0, start_cntl_g 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t start_cntl_g; \ start_cntl_g 392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G); start_cntl_g 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G); start_cntl_g 545 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G); start_cntl_g 574 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G); start_cntl_g 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); start_cntl_g 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); start_cntl_g 295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]); start_cntl_g 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);