stage_off         103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	int stage_off;
stage_off         109 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	stage_off = _stage_offset(ctx, stage);
stage_off         110 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	if (WARN_ON(stage_off < 0))
stage_off         114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);
stage_off         115 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
stage_off         122 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	int stage_off;
stage_off         127 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	stage_off = _stage_offset(ctx, stage);
stage_off         128 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	if (WARN_ON(stage_off < 0))
stage_off         131 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);
stage_off         132 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);
stage_off         133 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 	DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);