sspp 412 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .sspp = sdm845_sspp, sspp 662 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h struct dpu_sspp_cfg *sspp; sspp 116 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c enum dpu_sspp sspp) sspp 120 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c switch (sspp) { sspp 398 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c struct dpu_hw_pipe_cfg *sspp, sspp 406 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp sspp 412 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c sspp->layout.format); sspp 669 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c static struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, sspp 676 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c if ((sspp < SSPP_MAX) && catalog && addr && b) { sspp 678 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c if (sspp == catalog->sspp[i].id) { sspp 680 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b->blk_off = catalog->sspp[i].base; sspp 681 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b->length = catalog->sspp[i].len; sspp 684 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c return &catalog->sspp[i]; sspp 139 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_VIG0] = (value >> 4) & 0x3; sspp 140 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_VIG1] = (value >> 6) & 0x3; sspp 141 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_VIG2] = (value >> 8) & 0x3; sspp 142 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_VIG3] = (value >> 10) & 0x3; sspp 143 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB0] = (value >> 12) & 0x3; sspp 144 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB1] = (value >> 14) & 0x3; sspp 145 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB2] = (value >> 16) & 0x3; sspp 146 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB3] = (value >> 18) & 0x3; sspp 147 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA0] = (value >> 20) & 0x3; sspp 148 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA1] = (value >> 22) & 0x3; sspp 149 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA2] = (value >> 28) & 0x3; sspp 150 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA3] = (value >> 30) & 0x3; sspp 151 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x3; sspp 152 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3; sspp 236 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_VIG0] = (value >> 4) & 0x1; sspp 237 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_VIG1] = (value >> 6) & 0x1; sspp 238 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_VIG2] = (value >> 8) & 0x1; sspp 239 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_VIG3] = (value >> 10) & 0x1; sspp 240 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB0] = (value >> 12) & 0x1; sspp 241 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB1] = (value >> 14) & 0x1; sspp 242 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB2] = (value >> 16) & 0x1; sspp 243 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB3] = (value >> 18) & 0x1; sspp 244 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA0] = (value >> 20) & 0x1; sspp 245 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA1] = (value >> 22) & 0x1; sspp 246 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA2] = (value >> 28) & 0x1; sspp 247 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA3] = (value >> 30) & 0x1; sspp 248 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x1; sspp 249 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1; sspp 53 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h u8 sspp[SSPP_MAX]; sspp 101 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c status.sspp[i]); sspp 527 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) sspp 536 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c type, catalog->sspp[i].features, sspp 537 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); sspp 539 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c plane = dpu_plane_init(dev, catalog->sspp[i].id, type, sspp 645 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format, sspp 647 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp, sspp 657 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( enum dpu_sspp, sspp ) sspp 671 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __entry->sspp = sspp; sspp 684 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __entry->stage_idx, __entry->stage, __entry->sspp, sspp 1322 kernel/rcu/srcutree.c struct srcu_struct **sspp = mod->srcu_struct_ptrs; sspp 1326 kernel/rcu/srcutree.c ret = init_srcu_struct(*(sspp++)); sspp 1337 kernel/rcu/srcutree.c struct srcu_struct **sspp = mod->srcu_struct_ptrs; sspp 1340 kernel/rcu/srcutree.c cleanup_srcu_struct(*(sspp++));