sseu 1109 drivers/gpu/drm/i915/gem/i915_gem_context.c struct intel_sseu sseu) sseu 1125 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = intel_sseu_make_rpcs(rq->i915, &sseu); sseu 1133 drivers/gpu/drm/i915/gem/i915_gem_context.c gen8_modify_rpcs(struct intel_context *ce, struct intel_sseu sseu) sseu 1156 drivers/gpu/drm/i915/gem/i915_gem_context.c ret = gen8_emit_rpcs_config(rq, ce, sseu); sseu 1164 drivers/gpu/drm/i915/gem/i915_gem_context.c struct intel_sseu sseu) sseu 1175 drivers/gpu/drm/i915/gem/i915_gem_context.c if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) sseu 1178 drivers/gpu/drm/i915/gem/i915_gem_context.c ret = gen8_modify_rpcs(ce, sseu); sseu 1180 drivers/gpu/drm/i915/gem/i915_gem_context.c ce->sseu = sseu; sseu 1188 drivers/gpu/drm/i915/gem/i915_gem_context.c intel_context_reconfigure_sseu(struct intel_context *ce, struct intel_sseu sseu) sseu 1197 drivers/gpu/drm/i915/gem/i915_gem_context.c ret = __intel_context_reconfigure_sseu(ce, sseu); sseu 1209 drivers/gpu/drm/i915/gem/i915_gem_context.c const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu; sseu 1308 drivers/gpu/drm/i915/gem/i915_gem_context.c struct intel_sseu sseu; sseu 1342 drivers/gpu/drm/i915/gem/i915_gem_context.c ret = user_to_context_sseu(i915, &user_sseu, &sseu); sseu 1346 drivers/gpu/drm/i915/gem/i915_gem_context.c ret = intel_context_reconfigure_sseu(ce, sseu); sseu 1952 drivers/gpu/drm/i915/gem/i915_gem_context.c clone->engines[n]->sseu = ce->sseu; sseu 2195 drivers/gpu/drm/i915/gem/i915_gem_context.c user_sseu.slice_mask = ce->sseu.slice_mask; sseu 2196 drivers/gpu/drm/i915/gem/i915_gem_context.c user_sseu.subslice_mask = ce->sseu.subslice_mask; sseu 2197 drivers/gpu/drm/i915/gem/i915_gem_context.c user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice; sseu 2198 drivers/gpu/drm/i915/gem/i915_gem_context.c user_sseu.max_eus_per_subslice = ce->sseu.max_eus_per_subslice; sseu 839 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c unsigned int slices = hweight32(ce->engine->sseu.slice_mask); sseu 881 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c struct intel_sseu sseu) sseu 890 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c ret = __intel_context_reconfigure_sseu(ce, sseu); sseu 895 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c hweight32(sseu.slice_mask), spin); sseu 922 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c if (!RUNTIME_INFO(i915)->sseu.has_slice_pg) sseu 925 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c if (hweight32(engine->sseu.slice_mask) < 2) sseu 932 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c pg_sseu = engine->sseu; sseu 935 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); sseu 938 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c name, flags, hweight32(engine->sseu.slice_mask), sseu 974 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c ret = __sseu_test(name, flags, ce, obj, engine->sseu); sseu 984 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c ret = __sseu_test(name, flags, ce, obj, engine->sseu); sseu 233 drivers/gpu/drm/i915/gt/intel_context.c ce->sseu = engine->sseu; sseu 76 drivers/gpu/drm/i915/gt/intel_context_types.h struct intel_sseu sseu; sseu 607 drivers/gpu/drm/i915/gt/intel_engine_cs.c engine->sseu = sseu 608 drivers/gpu/drm/i915/gt/intel_engine_cs.c intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu); sseu 314 drivers/gpu/drm/i915/gt/intel_engine_types.h struct intel_sseu sseu; sseu 589 drivers/gpu/drm/i915/gt/intel_engine_types.h 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask) sseu 593 drivers/gpu/drm/i915/gt/intel_engine_types.h 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0]) sseu 1779 drivers/gpu/drm/i915/gt/intel_lrc.c intel_sseu_make_rpcs(engine->i915, &ce->sseu); sseu 12 drivers/gpu/drm/i915/gt/intel_sseu.c intel_sseu_subslice_total(const struct sseu_dev_info *sseu) sseu 16 drivers/gpu/drm/i915/gt/intel_sseu.c for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) sseu 17 drivers/gpu/drm/i915/gt/intel_sseu.c total += hweight8(sseu->subslice_mask[i]); sseu 23 drivers/gpu/drm/i915/gt/intel_sseu.c intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) sseu 25 drivers/gpu/drm/i915/gt/intel_sseu.c return hweight8(sseu->subslice_mask[slice]); sseu 31 drivers/gpu/drm/i915/gt/intel_sseu.c const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; sseu 32 drivers/gpu/drm/i915/gt/intel_sseu.c bool subslice_pg = sseu->has_subslice_pg; sseu 55 drivers/gpu/drm/i915/gt/intel_sseu.c ctx_sseu = intel_sseu_from_device_info(sseu); sseu 99 drivers/gpu/drm/i915/gt/intel_sseu.c subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) { sseu 112 drivers/gpu/drm/i915/gt/intel_sseu.c if (sseu->has_slice_pg) { sseu 140 drivers/gpu/drm/i915/gt/intel_sseu.c if (sseu->has_eu_pg) { sseu 54 drivers/gpu/drm/i915/gt/intel_sseu.h intel_sseu_from_device_info(const struct sseu_dev_info *sseu) sseu 57 drivers/gpu/drm/i915/gt/intel_sseu.h .slice_mask = sseu->slice_mask, sseu 58 drivers/gpu/drm/i915/gt/intel_sseu.h .subslice_mask = sseu->subslice_mask[0], sseu 59 drivers/gpu/drm/i915/gt/intel_sseu.h .min_eus_per_subslice = sseu->max_eus_per_subslice, sseu 60 drivers/gpu/drm/i915/gt/intel_sseu.h .max_eus_per_subslice = sseu->max_eus_per_subslice, sseu 67 drivers/gpu/drm/i915/gt/intel_sseu.h intel_sseu_subslice_total(const struct sseu_dev_info *sseu); sseu 70 drivers/gpu/drm/i915/gt/intel_sseu.h intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice); sseu 384 drivers/gpu/drm/i915/gt/intel_workarounds.c if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) sseu 393 drivers/gpu/drm/i915/gt/intel_workarounds.c ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; sseu 753 drivers/gpu/drm/i915/gt/intel_workarounds.c const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; sseu 787 drivers/gpu/drm/i915/gt/intel_workarounds.c if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { sseu 798 drivers/gpu/drm/i915/gt/intel_workarounds.c slice = fls(sseu->slice_mask) - 1; sseu 799 drivers/gpu/drm/i915/gt/intel_workarounds.c GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask)); sseu 800 drivers/gpu/drm/i915/gt/intel_workarounds.c subslice = fls(l3_en & sseu->subslice_mask[slice]); sseu 803 drivers/gpu/drm/i915/gt/intel_workarounds.c sseu->subslice_mask[slice], l3_en); sseu 101 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); sseu 2809 drivers/gpu/drm/i915/i915_debugfs.c intel_device_info_dump_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); sseu 3729 drivers/gpu/drm/i915/i915_debugfs.c struct sseu_dev_info *sseu) sseu 3748 drivers/gpu/drm/i915/i915_debugfs.c sseu->slice_mask = BIT(0); sseu 3749 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[0] |= BIT(ss); sseu 3754 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_total += eu_cnt; sseu 3755 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_per_subslice = max_t(unsigned int, sseu 3756 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_per_subslice, eu_cnt); sseu 3762 drivers/gpu/drm/i915/i915_debugfs.c struct sseu_dev_info *sseu) sseu 3769 drivers/gpu/drm/i915/i915_debugfs.c for (s = 0; s < info->sseu.max_slices; s++) { sseu 3791 drivers/gpu/drm/i915/i915_debugfs.c for (s = 0; s < info->sseu.max_slices; s++) { sseu 3796 drivers/gpu/drm/i915/i915_debugfs.c sseu->slice_mask |= BIT(s); sseu 3797 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[s] = info->sseu.subslice_mask[s]; sseu 3799 drivers/gpu/drm/i915/i915_debugfs.c for (ss = 0; ss < info->sseu.max_subslices; ss++) { sseu 3808 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_total += eu_cnt; sseu 3809 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_per_subslice = max_t(unsigned int, sseu 3810 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_per_subslice, sseu 3818 drivers/gpu/drm/i915/i915_debugfs.c struct sseu_dev_info *sseu) sseu 3825 drivers/gpu/drm/i915/i915_debugfs.c for (s = 0; s < info->sseu.max_slices; s++) { sseu 3840 drivers/gpu/drm/i915/i915_debugfs.c for (s = 0; s < info->sseu.max_slices; s++) { sseu 3845 drivers/gpu/drm/i915/i915_debugfs.c sseu->slice_mask |= BIT(s); sseu 3848 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[s] = sseu 3849 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; sseu 3851 drivers/gpu/drm/i915/i915_debugfs.c for (ss = 0; ss < info->sseu.max_subslices; ss++) { sseu 3859 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[s] |= BIT(ss); sseu 3864 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_total += eu_cnt; sseu 3865 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_per_subslice = max_t(unsigned int, sseu 3866 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_per_subslice, sseu 3874 drivers/gpu/drm/i915/i915_debugfs.c struct sseu_dev_info *sseu) sseu 3879 drivers/gpu/drm/i915/i915_debugfs.c sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; sseu 3881 drivers/gpu/drm/i915/i915_debugfs.c if (sseu->slice_mask) { sseu 3882 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_per_subslice = sseu 3883 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice; sseu 3884 drivers/gpu/drm/i915/i915_debugfs.c for (s = 0; s < fls(sseu->slice_mask); s++) { sseu 3885 drivers/gpu/drm/i915/i915_debugfs.c sseu->subslice_mask[s] = sseu 3886 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; sseu 3888 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_total = sseu->eu_per_subslice * sseu 3889 drivers/gpu/drm/i915/i915_debugfs.c intel_sseu_subslice_total(sseu); sseu 3892 drivers/gpu/drm/i915/i915_debugfs.c for (s = 0; s < fls(sseu->slice_mask); s++) { sseu 3894 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s]; sseu 3896 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_total -= hweight8(subslice_7eu); sseu 3902 drivers/gpu/drm/i915/i915_debugfs.c const struct sseu_dev_info *sseu) sseu 3909 drivers/gpu/drm/i915/i915_debugfs.c sseu->slice_mask); sseu 3911 drivers/gpu/drm/i915/i915_debugfs.c hweight8(sseu->slice_mask)); sseu 3913 drivers/gpu/drm/i915/i915_debugfs.c intel_sseu_subslice_total(sseu)); sseu 3914 drivers/gpu/drm/i915/i915_debugfs.c for (s = 0; s < fls(sseu->slice_mask); s++) { sseu 3916 drivers/gpu/drm/i915/i915_debugfs.c s, intel_sseu_subslices_per_slice(sseu, s)); sseu 3919 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_total); sseu 3921 drivers/gpu/drm/i915/i915_debugfs.c sseu->eu_per_subslice); sseu 3928 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); sseu 3931 drivers/gpu/drm/i915/i915_debugfs.c yesno(sseu->has_slice_pg)); sseu 3933 drivers/gpu/drm/i915/i915_debugfs.c yesno(sseu->has_subslice_pg)); sseu 3935 drivers/gpu/drm/i915/i915_debugfs.c yesno(sseu->has_eu_pg)); sseu 3941 drivers/gpu/drm/i915/i915_debugfs.c struct sseu_dev_info sseu; sseu 3948 drivers/gpu/drm/i915/i915_debugfs.c i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu); sseu 3951 drivers/gpu/drm/i915/i915_debugfs.c memset(&sseu, 0, sizeof(sseu)); sseu 3952 drivers/gpu/drm/i915/i915_debugfs.c sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices; sseu 3953 drivers/gpu/drm/i915/i915_debugfs.c sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices; sseu 3954 drivers/gpu/drm/i915/i915_debugfs.c sseu.max_eus_per_subslice = sseu 3955 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice; sseu 3959 drivers/gpu/drm/i915/i915_debugfs.c cherryview_sseu_device_status(dev_priv, &sseu); sseu 3961 drivers/gpu/drm/i915/i915_debugfs.c broadwell_sseu_device_status(dev_priv, &sseu); sseu 3963 drivers/gpu/drm/i915/i915_debugfs.c gen9_sseu_device_status(dev_priv, &sseu); sseu 3965 drivers/gpu/drm/i915/i915_debugfs.c gen10_sseu_device_status(dev_priv, &sseu); sseu 3968 drivers/gpu/drm/i915/i915_debugfs.c i915_print_sseu_info(m, false, &sseu); sseu 13 drivers/gpu/drm/i915/i915_getparam.c const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; sseu 71 drivers/gpu/drm/i915/i915_getparam.c value = intel_sseu_subslice_total(sseu); sseu 76 drivers/gpu/drm/i915/i915_getparam.c value = sseu->eu_total; sseu 93 drivers/gpu/drm/i915/i915_getparam.c value = sseu->min_eu_in_pool; sseu 144 drivers/gpu/drm/i915/i915_getparam.c value = sseu->slice_mask; sseu 149 drivers/gpu/drm/i915/i915_getparam.c value = sseu->subslice_mask[0]; sseu 601 drivers/gpu/drm/i915/i915_gpu_error.c intel_device_info_dump_topology(&runtime->sseu, &p); sseu 1707 drivers/gpu/drm/i915/i915_perf.c intel_sseu_make_rpcs(i915, &ce->sseu)); sseu 1820 drivers/gpu/drm/i915/i915_perf.c flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu); sseu 1935 drivers/gpu/drm/i915/i915_perf.c regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu); sseu 37 drivers/gpu/drm/i915/i915_query.c const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; sseu 40 drivers/gpu/drm/i915/i915_query.c u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices); sseu 41 drivers/gpu/drm/i915/i915_query.c u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); sseu 47 drivers/gpu/drm/i915/i915_query.c if (sseu->max_slices == 0) sseu 50 drivers/gpu/drm/i915/i915_query.c BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); sseu 52 drivers/gpu/drm/i915/i915_query.c slice_length = sizeof(sseu->slice_mask); sseu 53 drivers/gpu/drm/i915/i915_query.c subslice_length = sseu->max_slices * subslice_stride; sseu 54 drivers/gpu/drm/i915/i915_query.c eu_length = sseu->max_slices * sseu->max_subslices * eu_stride; sseu 67 drivers/gpu/drm/i915/i915_query.c topo.max_slices = sseu->max_slices; sseu 68 drivers/gpu/drm/i915/i915_query.c topo.max_subslices = sseu->max_subslices; sseu 69 drivers/gpu/drm/i915/i915_query.c topo.max_eus_per_subslice = sseu->max_eus_per_subslice; sseu 81 drivers/gpu/drm/i915/i915_query.c &sseu->slice_mask, slice_length)) sseu 86 drivers/gpu/drm/i915/i915_query.c sseu->subslice_mask, subslice_length)) sseu 92 drivers/gpu/drm/i915/i915_query.c sseu->eu_mask, eu_length)) sseu 88 drivers/gpu/drm/i915/intel_device_info.c static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) sseu 93 drivers/gpu/drm/i915/intel_device_info.c hweight8(sseu->slice_mask), sseu->slice_mask); sseu 94 drivers/gpu/drm/i915/intel_device_info.c drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); sseu 95 drivers/gpu/drm/i915/intel_device_info.c for (s = 0; s < sseu->max_slices; s++) { sseu 97 drivers/gpu/drm/i915/intel_device_info.c s, intel_sseu_subslices_per_slice(sseu, s), sseu 98 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s]); sseu 100 drivers/gpu/drm/i915/intel_device_info.c drm_printf(p, "EU total: %u\n", sseu->eu_total); sseu 101 drivers/gpu/drm/i915/intel_device_info.c drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); sseu 103 drivers/gpu/drm/i915/intel_device_info.c yesno(sseu->has_slice_pg)); sseu 105 drivers/gpu/drm/i915/intel_device_info.c yesno(sseu->has_subslice_pg)); sseu 106 drivers/gpu/drm/i915/intel_device_info.c drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); sseu 112 drivers/gpu/drm/i915/intel_device_info.c sseu_dump(&info->sseu, p); sseu 118 drivers/gpu/drm/i915/intel_device_info.c static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, sseu 121 drivers/gpu/drm/i915/intel_device_info.c int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); sseu 122 drivers/gpu/drm/i915/intel_device_info.c int slice_stride = sseu->max_subslices * subslice_stride; sseu 127 drivers/gpu/drm/i915/intel_device_info.c static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, sseu 130 drivers/gpu/drm/i915/intel_device_info.c int i, offset = sseu_eu_idx(sseu, slice, subslice); sseu 133 drivers/gpu/drm/i915/intel_device_info.c for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) { sseu 134 drivers/gpu/drm/i915/intel_device_info.c eu_mask |= ((u16)sseu->eu_mask[offset + i]) << sseu 141 drivers/gpu/drm/i915/intel_device_info.c static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, sseu 144 drivers/gpu/drm/i915/intel_device_info.c int i, offset = sseu_eu_idx(sseu, slice, subslice); sseu 146 drivers/gpu/drm/i915/intel_device_info.c for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) { sseu 147 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_mask[offset + i] = sseu 152 drivers/gpu/drm/i915/intel_device_info.c void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, sseu 157 drivers/gpu/drm/i915/intel_device_info.c if (sseu->max_slices == 0) { sseu 162 drivers/gpu/drm/i915/intel_device_info.c for (s = 0; s < sseu->max_slices; s++) { sseu 164 drivers/gpu/drm/i915/intel_device_info.c s, intel_sseu_subslices_per_slice(sseu, s), sseu 165 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s]); sseu 167 drivers/gpu/drm/i915/intel_device_info.c for (ss = 0; ss < sseu->max_subslices; ss++) { sseu 168 drivers/gpu/drm/i915/intel_device_info.c u16 enabled_eus = sseu_get_eus(sseu, s, ss); sseu 176 drivers/gpu/drm/i915/intel_device_info.c static u16 compute_eu_total(const struct sseu_dev_info *sseu) sseu 180 drivers/gpu/drm/i915/intel_device_info.c for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) sseu 181 drivers/gpu/drm/i915/intel_device_info.c total += hweight8(sseu->eu_mask[i]); sseu 188 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; sseu 195 drivers/gpu/drm/i915/intel_device_info.c sseu->max_slices = 1; sseu 196 drivers/gpu/drm/i915/intel_device_info.c sseu->max_subslices = 4; sseu 197 drivers/gpu/drm/i915/intel_device_info.c sseu->max_eus_per_subslice = 8; sseu 199 drivers/gpu/drm/i915/intel_device_info.c sseu->max_slices = 1; sseu 200 drivers/gpu/drm/i915/intel_device_info.c sseu->max_subslices = 8; sseu 201 drivers/gpu/drm/i915/intel_device_info.c sseu->max_eus_per_subslice = 8; sseu 206 drivers/gpu/drm/i915/intel_device_info.c ss_en_mask = BIT(sseu->max_subslices) - 1; sseu 209 drivers/gpu/drm/i915/intel_device_info.c for (s = 0; s < sseu->max_slices; s++) { sseu 211 drivers/gpu/drm/i915/intel_device_info.c int ss_idx = sseu->max_subslices * s; sseu 214 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask |= BIT(s); sseu 215 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask; sseu 216 drivers/gpu/drm/i915/intel_device_info.c for (ss = 0; ss < sseu->max_subslices; ss++) { sseu 217 drivers/gpu/drm/i915/intel_device_info.c if (sseu->subslice_mask[s] & BIT(ss)) sseu 218 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, s, ss, eu_en); sseu 222 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_per_subslice = hweight8(eu_en); sseu 223 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_total = compute_eu_total(sseu); sseu 226 drivers/gpu/drm/i915/intel_device_info.c sseu->has_slice_pg = 1; sseu 227 drivers/gpu/drm/i915/intel_device_info.c sseu->has_subslice_pg = 1; sseu 228 drivers/gpu/drm/i915/intel_device_info.c sseu->has_eu_pg = 1; sseu 233 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; sseu 239 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> sseu 241 drivers/gpu/drm/i915/intel_device_info.c sseu->max_slices = 6; sseu 242 drivers/gpu/drm/i915/intel_device_info.c sseu->max_subslices = 4; sseu 243 drivers/gpu/drm/i915/intel_device_info.c sseu->max_eus_per_subslice = 8; sseu 253 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = subslice_mask; sseu 254 drivers/gpu/drm/i915/intel_device_info.c for (s = 1; s < sseu->max_slices; s++) sseu 255 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] = subslice_mask & 0x3; sseu 259 drivers/gpu/drm/i915/intel_device_info.c for (ss = 0; ss < sseu->max_subslices; ss++) sseu 260 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); sseu 262 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); sseu 264 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); sseu 266 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); sseu 267 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); sseu 269 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); sseu 271 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); sseu 273 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); sseu 274 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); sseu 276 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); sseu 278 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); sseu 283 drivers/gpu/drm/i915/intel_device_info.c for (s = 0; s < sseu->max_slices; s++) { sseu 284 drivers/gpu/drm/i915/intel_device_info.c for (ss = 0; ss < sseu->max_subslices; ss++) { sseu 285 drivers/gpu/drm/i915/intel_device_info.c if (sseu_get_eus(sseu, s, ss) == 0) sseu 286 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] &= ~BIT(ss); sseu 290 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_total = compute_eu_total(sseu); sseu 298 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? sseu 299 drivers/gpu/drm/i915/intel_device_info.c DIV_ROUND_UP(sseu->eu_total, sseu 300 drivers/gpu/drm/i915/intel_device_info.c intel_sseu_subslice_total(sseu)) : sseu 304 drivers/gpu/drm/i915/intel_device_info.c sseu->has_slice_pg = 1; sseu 305 drivers/gpu/drm/i915/intel_device_info.c sseu->has_subslice_pg = 1; sseu 306 drivers/gpu/drm/i915/intel_device_info.c sseu->has_eu_pg = 1; sseu 311 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; sseu 316 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = BIT(0); sseu 317 drivers/gpu/drm/i915/intel_device_info.c sseu->max_slices = 1; sseu 318 drivers/gpu/drm/i915/intel_device_info.c sseu->max_subslices = 2; sseu 319 drivers/gpu/drm/i915/intel_device_info.c sseu->max_eus_per_subslice = 8; sseu 328 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] |= BIT(0); sseu 329 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 0, 0, ~disabled_mask); sseu 339 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] |= BIT(1); sseu 340 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, 0, 1, ~disabled_mask); sseu 343 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_total = compute_eu_total(sseu); sseu 349 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? sseu 350 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_total / sseu 351 drivers/gpu/drm/i915/intel_device_info.c intel_sseu_subslice_total(sseu) : sseu 358 drivers/gpu/drm/i915/intel_device_info.c sseu->has_slice_pg = 0; sseu 359 drivers/gpu/drm/i915/intel_device_info.c sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; sseu 360 drivers/gpu/drm/i915/intel_device_info.c sseu->has_eu_pg = (sseu->eu_per_subslice > 2); sseu 366 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; sseu 372 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; sseu 375 drivers/gpu/drm/i915/intel_device_info.c sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3; sseu 376 drivers/gpu/drm/i915/intel_device_info.c sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4; sseu 377 drivers/gpu/drm/i915/intel_device_info.c sseu->max_eus_per_subslice = 8; sseu 383 drivers/gpu/drm/i915/intel_device_info.c subslice_mask = (1 << sseu->max_subslices) - 1; sseu 391 drivers/gpu/drm/i915/intel_device_info.c for (s = 0; s < sseu->max_slices; s++) { sseu 392 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->slice_mask & BIT(s))) sseu 396 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] = subslice_mask; sseu 399 drivers/gpu/drm/i915/intel_device_info.c for (ss = 0; ss < sseu->max_subslices; ss++) { sseu 403 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->subslice_mask[s] & BIT(ss))) sseu 409 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); sseu 411 drivers/gpu/drm/i915/intel_device_info.c eu_per_ss = sseu->max_eus_per_subslice - sseu 420 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_7eu[s] |= BIT(ss); sseu 424 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_total = compute_eu_total(sseu); sseu 433 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? sseu 434 drivers/gpu/drm/i915/intel_device_info.c DIV_ROUND_UP(sseu->eu_total, sseu 435 drivers/gpu/drm/i915/intel_device_info.c intel_sseu_subslice_total(sseu)) : sseu 445 drivers/gpu/drm/i915/intel_device_info.c sseu->has_slice_pg = sseu 446 drivers/gpu/drm/i915/intel_device_info.c !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; sseu 447 drivers/gpu/drm/i915/intel_device_info.c sseu->has_subslice_pg = sseu 448 drivers/gpu/drm/i915/intel_device_info.c IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; sseu 449 drivers/gpu/drm/i915/intel_device_info.c sseu->has_eu_pg = sseu->eu_per_subslice > 2; sseu 452 drivers/gpu/drm/i915/intel_device_info.c #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) sseu 453 drivers/gpu/drm/i915/intel_device_info.c info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; sseu 455 drivers/gpu/drm/i915/intel_device_info.c sseu->min_eu_in_pool = 0; sseu 458 drivers/gpu/drm/i915/intel_device_info.c sseu->min_eu_in_pool = 3; sseu 460 drivers/gpu/drm/i915/intel_device_info.c sseu->min_eu_in_pool = 6; sseu 462 drivers/gpu/drm/i915/intel_device_info.c sseu->min_eu_in_pool = 9; sseu 470 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; sseu 475 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; sseu 476 drivers/gpu/drm/i915/intel_device_info.c sseu->max_slices = 3; sseu 477 drivers/gpu/drm/i915/intel_device_info.c sseu->max_subslices = 3; sseu 478 drivers/gpu/drm/i915/intel_device_info.c sseu->max_eus_per_subslice = 8; sseu 484 drivers/gpu/drm/i915/intel_device_info.c subslice_mask = GENMASK(sseu->max_subslices - 1, 0); sseu 500 drivers/gpu/drm/i915/intel_device_info.c for (s = 0; s < sseu->max_slices; s++) { sseu 501 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->slice_mask & BIT(s))) sseu 505 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[s] = subslice_mask; sseu 507 drivers/gpu/drm/i915/intel_device_info.c for (ss = 0; ss < sseu->max_subslices; ss++) { sseu 511 drivers/gpu/drm/i915/intel_device_info.c if (!(sseu->subslice_mask[s] & BIT(ss))) sseu 516 drivers/gpu/drm/i915/intel_device_info.c eu_disable[s] >> (ss * sseu->max_eus_per_subslice); sseu 518 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); sseu 525 drivers/gpu/drm/i915/intel_device_info.c if (sseu->max_eus_per_subslice - n_disabled == 7) sseu 526 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_7eu[s] |= 1 << ss; sseu 530 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_total = compute_eu_total(sseu); sseu 537 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? sseu 538 drivers/gpu/drm/i915/intel_device_info.c DIV_ROUND_UP(sseu->eu_total, sseu 539 drivers/gpu/drm/i915/intel_device_info.c intel_sseu_subslice_total(sseu)) : sseu 546 drivers/gpu/drm/i915/intel_device_info.c sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; sseu 547 drivers/gpu/drm/i915/intel_device_info.c sseu->has_subslice_pg = 0; sseu 548 drivers/gpu/drm/i915/intel_device_info.c sseu->has_eu_pg = 0; sseu 553 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; sseu 566 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = BIT(0); sseu 567 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = BIT(0); sseu 570 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = BIT(0); sseu 571 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = BIT(0) | BIT(1); sseu 574 drivers/gpu/drm/i915/intel_device_info.c sseu->slice_mask = BIT(0) | BIT(1); sseu 575 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[0] = BIT(0) | BIT(1); sseu 576 drivers/gpu/drm/i915/intel_device_info.c sseu->subslice_mask[1] = BIT(0) | BIT(1); sseu 580 drivers/gpu/drm/i915/intel_device_info.c sseu->max_slices = hweight8(sseu->slice_mask); sseu 581 drivers/gpu/drm/i915/intel_device_info.c sseu->max_subslices = hweight8(sseu->subslice_mask[0]); sseu 590 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_per_subslice = 10; sseu 593 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_per_subslice = 8; sseu 596 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_per_subslice = 6; sseu 599 drivers/gpu/drm/i915/intel_device_info.c sseu->max_eus_per_subslice = sseu->eu_per_subslice; sseu 601 drivers/gpu/drm/i915/intel_device_info.c for (s = 0; s < sseu->max_slices; s++) { sseu 602 drivers/gpu/drm/i915/intel_device_info.c for (ss = 0; ss < sseu->max_subslices; ss++) { sseu 603 drivers/gpu/drm/i915/intel_device_info.c sseu_set_eus(sseu, s, ss, sseu 604 drivers/gpu/drm/i915/intel_device_info.c (1UL << sseu->eu_per_subslice) - 1); sseu 608 drivers/gpu/drm/i915/intel_device_info.c sseu->eu_total = compute_eu_total(sseu); sseu 611 drivers/gpu/drm/i915/intel_device_info.c sseu->has_slice_pg = 0; sseu 612 drivers/gpu/drm/i915/intel_device_info.c sseu->has_subslice_pg = 0; sseu 613 drivers/gpu/drm/i915/intel_device_info.c sseu->has_eu_pg = 0; sseu 210 drivers/gpu/drm/i915/intel_device_info.h struct sseu_dev_info sseu; sseu 231 drivers/gpu/drm/i915/intel_device_info.h void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, sseu 7566 drivers/gpu/drm/i915/intel_pm.c switch (RUNTIME_INFO(dev_priv)->sseu.eu_total) {